CS61C L24 Latches (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 24 – Latches Yak!   The Honeynet project uses “honeypot” PCs & monitors how long it takes (sec-min) for them to be hacked and what happens. 1 Mebi “botnets” are used for spam, viruses, DDoS, Google AdSense, hacking gambling, id theft! news.bbc.co.uk/2/hi/technology/ stm

CS61C L24 Latches (2) Garcia © UCB Last time: Extremely Clever Subtractor xora b + ++ (unsigned) overflow (signed)

CS61C L24 Latches (3) Garcia © UCB 2-Input Multiplexor (MUX) Review Definition Symbol C A B 0 1 D

CS61C L24 Latches (4) Garcia © UCB Review… Use muxes to select among input S input bits selects 2 S inputs Each input can be n-bits wide, indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N-bit adder-subtractor done using N 1-bit adders with XOR gates on input XOR serves as conditional inverter

CS61C L24 Latches (5) Garcia © UCB Combinational Logic from 10 miles up CL circuits simply compute a binary function (e.g., from truthtable) Once the inputs go away, the outputs go away, nothing is saved, no STATE Similar to a function in Scheme with no set! or define to save anything How does the computer remember data? [e.g., for registers] X Y X Y Z (define (xor x y) (or (and (not x) y) (and x (not y))))

CS61C L24 Latches (6) Garcia © UCB State Circuits Overview State circuits have feedback, e.g. Output is function of inputs + fed-back signals. Feedback signals are the circuit's state. What aspects of this circuit might cause complications? Combi- national Logic

CS61C L24 Latches (7) Garcia © UCB A simpler state circuit: two inverters When started up, it's internally stable. Provide an or gate for coordination: What's the result? ! How do we set to 0?

CS61C L24 Latches (8) Garcia © UCB 0 Hold! An R-S latch (cross-coupled NOR gates) S means “set” (to 1), R means “reset” (to 0). Adding Q’ gives standard RS-latch: Truth table S R Q 0 0 hold (keep value) unstable A B NOR _Q_Q Hold! 0

CS61C L24 Latches (9) Garcia © UCB An R-S latch (in detail) Truth table _ S R Q Q Q(t+  t) hold hold reset reset set set x x unstable x x unstable A B NOR

CS61C L24 Latches (10) Garcia © UCB R-S latch in scheme (define (rs-latch r s) (define (rsl-h q qbar) (rsl-h (nor r qbar) (nor q s))) (rsl-h #t #f)) A B NOR It’s really just… recursion! (demo)

CS61C L24 Latches (11) Garcia © UCB State diagram States represent possible output values. Transitions represent changes between states based on inputs. Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 SR=00 SR=11 SR=00 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=10 SR=01 SR=10 SR=11

CS61C L24 Latches (12) Garcia © UCB What does it mean to “clobber” midterm? You STILL have to take the final even if you aced the midterm! The final will contain midterm-material Qs and new, post-midterm Qs They will be graded separately If you do “better” on the midterm-material, we will clobber your midterm with the “new” score! If you do worse, midterm unchanged. What does “better” mean? Better w.r.t. Standard Deviations around mean What does “new” mean? Score based on remapping St. Dev. score on final midterm-material to midterm score St. Dev.

CS61C L24 Latches (13) Garcia © UCB “Clobber the midterm” example Midterm Mean: 47 Standard Deviation: 14 You got a 33, one  below Final Midterm-Material Questions Mean: 40 Standard Deviation: 20 You got a 60, one  above Your new midterm score is now mean +  = = 61 (~ double your old score)!

CS61C L24 Latches (14) Garcia © UCB Controlling R-S latch with a clock Can't change R and S while clock is active. Clocked latches are called flip-flops. A B NOR

CS61C L24 Latches (15) Garcia © UCB D flip-flop are what we really use Inputs C (clock) and D. When C is 1, latch open, output = D (even if it changes, “transparent latch”) When C is 0, latch closed, output = stored value. C D AND

CS61C L24 Latches (16) Garcia © UCB D flip-flop details We don’t like transparent latches We can build them so that the latch is only open for an instant, on the rising edge of a clock (as it goes from 0  1) D C Q Timing Diagram

CS61C L24 Latches (17) Garcia © UCB C P Q 0 1 D DC 0P 1Q But do you really understand NORs? If one input is 1, what is a NOR? If one input is 0, what is a NOR? A B NOR A B NOR A 0B’ 10 A _B_B 0 NOR

CS61C L24 Latches (18) Garcia © UCB C P Q 0 1 D DC 0P 1Q But do you really understand NANDs? If one input is 1, what is a NAND? If one input is 0, what is a NAND? A B NAND A NAND 01 1B’ A 1 _B_B NAND A B

CS61C L24 Latches (19) Garcia © UCB Peer instruction Pick the truth table that results from substituting NAND gates for the NOR gates in the R-S latch: A B Q 0 0 hold undef A B Q 0 0 hold undef A B Q 0 0 undef hold A B Q 0 0 undef hold 1234 A B NAND A B NOR

CS61C L24 Latches (20) Garcia © UCB Peer Instruction A. (a+b) (a+b) = b B. N-input gates can be thought of cascaded 2- input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS61C L24 Latches (21) Garcia © UCB A. (next slide) B. (next slide) C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT. ° NOR(a,a)= a+a = aa = a ° Using this NOT, can we make a NOR an OR? An And? ° TRUE Peer Instruction Answer A. (a+b) (a+b) = b B. N-input gates can be thought of cascaded 2- input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS61C L24 Latches (22) Garcia © UCB A. (a+b) (a+b) =?= b (a+b)(a+b) aa+ab+ba+bbdistribution 0+b(a+a)+bcomplimentarity, commutativity, distribution, idempotent b(1)+bidentity, complimentarity b+bidentity bidempotent Peer Instruction Answer (A) TRUE

CS61C L24 Latches (23) Garcia © UCB A. B. N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND…FALSE Let’s confirm! CORRECT 3-input XYZ|AND|OR|XOR|NAND 000| 0 |0 | 0 | 1 001| 0 |1 | 1 | 1 010| 0 |1 | 1 | 1 011| 0 |1 | 0 | 1 100| 0 |1 | 1 | 1 101| 0 |1 | 0 | 1 110| 0 |1 | 0 | 1 111| 1 |1 | 1 | 0 CORRECT 2-input YZ|AND|OR|XOR|NAND 00| 0 |0 | 0 | 1 01| 0 |1 | 1 | 1 10| 0 |1 | 1 | 1 11| 1 |1 | 0 | Peer Instruction Answer (B)

CS61C L24 Latches (24) Garcia © UCB Peer Instruction A. Truth table for mux with 4-bits of signals has 2 4 rows B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS61C L24 Latches (25) Garcia © UCB Peer Instruction Answer A. Truth table for mux with 4-bits of signals is 2 4 rows long B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT A. Truth table for mux with 4-bits of signals controls 16 inputs, for a total of 20 inputs, so truth table is 2 20 rows…FALSE B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl … TRUE C. What about the cascading carry? FALSE

CS61C L24 Latches (26) Garcia © UCB “And In conclusion…” We use feedback to maintain state RS-Latch the simplest memory element We’re not allowed to assert both R and S Clocks tell us when latches change D-FlipFlops used to build Register files