Nanotechnology: Spatial Computing Using Molecular Electronics Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater

SSS April 20, Intersection of Three Areas Reconfigurable computing Nanotechnology Computer architecture

SSS April 20, Prophecies, A Risky Endeavor I think there is a world market for maybe five computers. --- T. J. Watson 640K ought to be enough for everybody. --- Bill Gates There is no reason anyone would want a computer in their home. --- Ken Olson I will propose this semester. --- Anonymous There is not the slightest indication that nuclear energy will ever be obtainable. --- Albert Einstein

SSS April 20, Moore’s Law

SSS April 20, Moore’s Second Law Plant costMask cost generation X 1000$

SSS April 20, Our Proposal Nanotechnology + cheap + high-density + low-power – unreliable Computer architecture + vast body of knowledge – expensive – high-power Reconfigurable Computing + defect tolerant + high performance – low density _ _ _ _

SSS April 20, Paradigm Shift Executable Configuration Complex fixed chip + Program Dense, regular structure + Configuration

SSS April 20, Outline Introduction Reconfigurable computing Nanotechnology Nano-architecture proposal Preliminary results Conclusions and Future Work

SSS April 20, Reconfigurable Computing Back to ENIAC-style computing Synthesize one machine to solve one problem

SSS April 20, Island-Style RC Architecture Universal gates and/or storage elements Interconnection network Programmable Switches

SSS April 20, Switch controlled by a 1-bit RAM cell Universal gate = RAM a0 a1 a0 a1 data a1 & a2 0 data in control Main RC Ingredient: RAM Cell

SSS April 20, Place and Route int reverse(int x) { int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; } int func(int* a,int *b) { int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b

SSS April 20, Kernel Speedup Using PipeRench ATR Cordic DCT DCT-2D FIR IDEA Nqueens Over PopCount Times Over 300Mhz UltraSparc-II

SSS April 20, Defect Tolerance Despite having >70% of the chips defective, Teramac works flawlessly. Compilation has two phases: defect detection through self-testing placement for defect-avoidance

SSS April 20, Outline Introduction Reconfigurable computing Nanotechnology Nano-architecture proposal Preliminary results Conclusions and Future work

SSS April 20, Nanotechnology

SSS April 20, Predicted Features Low Power: gates use less than 2 W (compare to 3x10 7 transistors using 100 W in CMOS) Low cost (nanocents/gate) Small size (10 5 factor area gain) Nano-RAM cell In yellow: a CMOS RAM cell.

SSS April 20, Nano-wires carbon nanotubues, Si, metal >2nm diameter, up to mm length excellent electrical properties A carbon nanotube: one molecule

SSS April 20, Nano-switch

SSS April 20, Nano-switch Between Nano-wires

SSS April 20, Self-assembly

SSS April 20, No Complex Irregular Structures

SSS April 20, No Three-Terminal Devices

SSS April 20, Diode-resistor Logic V DD Output Input 1 Input 2 A * B V AND B A A ^ B VVV AND A B A B A * B Nano-implementationElectrical equivalent

SSS April 20, Nanoscale Latches D clock dataout Provide: signal restoration (amplification) clocking (synchronization) memory

SSS April 20, High Defect Rate

SSS April 20, Outline Introduction Reconfigurable computing Nanotechnology Nano-architecture proposal Preliminary results Conclusions and future work

SSS April 20, The nanoBlock (3-in to 3-out Logic) +Vdd Gnd clk Inputs Outputs CMOS clk

SSS April 20, Interconnecting nanoBlocks Switch block

SSS April 20, Global View

SSS April 20, Control cluster long-lines Many Clusters = nanoFabric

SSS April 20, Compilation 1.Program 2.Split-phase Abstract Machines 3.Configurations placed independently 4.Placement on chip int reverse(int x) { int k,r=0; for (k=0; k > 1; r = r << 1; } } Computations & local storage Unknown latency ops.

SSS April 20, Outline Introduction Reconfigurable Hardware Nanotechnology Nano-architecture proposal Preliminary results Conclusions and Future work

SSS April 20, A graph of the whole program execution: A Limit Study of Performance Memory word Basic block Memory write Memory read Control-flow transfer

SSS April 20, Area (10 6 units/cm 2 available)

SSS April 20, Typical Program Graph (g721_e) Control flow transfer 100% memory cluster Memory reads 100% code cluster

SSS April 20, Typical Program Graph (g721_e) Control flow transfer memory Memory reads code memcpy

SSS April 20, Program Graph After Inlining memcpy memcpy

SSS April 20, Application Slowdown

SSS April 20, How Time Is Spent No caches: reads expensive No speculation

SSS April 20, Future Work Better nano-devices More accurate hardware models in simulations Compilation technology

SSS April 20, Conclusions Electronic nanotechnology promises to transcend the limitations of CMOS Nanofabrics are very well suited to reconfigurable computation gate designs can be managed through hierarchies of abstract machines