7-Segment Display DIO1 Board. Digilab2 – DIO1 Boards Four 7-segment displays A0A1A2A3.

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Presentation transcript:

7-Segment Display DIO1 Board

Digilab2 – DIO1 Boards Four 7-segment displays A0A1A2A3

DIO1 Board – Common Anodes A0 A1 A2 A3 AtoG(6:0) Pins

Multiplex displays

Multiplex displays

Multiplex displays

Multiplex displays

x7seg

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity x7seg is Port ( x : in std_logic_vector(15 downto 0); cclk, clr : in std_logic; AtoG : out std_logic_vector(6 downto 0); A : out std_logic_vector(3 downto 0) ); end x7seg; x7seg.vhd

architecture arch_x7seg of x7seg is signal digit : std_logic_vector(3 downto 0); signal count : std_logic_vector(1 downto 0); begin

ctr2bit: process(cclk,clr) begin if(clr = '1') then count <= "00"; elsif(cclk'event and cclk = '1') then count <= count + 1; end if; end process;

-- MUX4 with count select digit <= x(15 downto 12) when "00", x(11 downto 8) when "01", x(7 downto 4) when "10", x(3 downto 0) when others;

-- seg7dec with digit select AtoG <=" " when "0001",--1 " " when "0010",--2 " " when "0011",--3 " " when "0100",--4 " " when "0101",--5 " " when "0110",--6 " " when "0111",--7 " " when "1000",--8 " " when "1001",--9 " " when "1010",--A " " when "1011",--b " " when "1100",--C " " when "1101",--d " " when "1110",--E " " when "1111",--F " " when others;--0

Acode: process(count) begin A '0'); A(conv_integer(count)) <= '1'; end process; end arch_x7seg; Example: count = 10 A(2) = 1 A(0) = A(1) = A(3) = 0 A(3:0) = 0100

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity x7seg_test is port ( mclk : in STD_LOGIC; bn : in STD_LOGIC; led: out std_logic; ldg : out STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); AtoG : out STD_LOGIC_VECTOR(6 downto 0); A : out STD_LOGIC_VECTOR(3 downto 0) ); end x7seg_test; x7seg_test.vhd

architecture x7seg_test_arch of x7seg_test is -- System Library Components component IBUFG port ( I : in STD_LOGIC; O : out std_logic ); end component; component x7seg port ( x : in std_logic_vector(15 downto 0); cclk, clr : in std_logic; AtoG : out std_logic_vector(6 downto 0); A : out std_logic_vector(3 downto 0) ); end component;

signal clr, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(23 downto 0); signal fix: std_logic_vector(7 downto 0); begin U00:IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74HC373 latch clr <= bnbuf;

-- Divide the master clock (50Mhz) down to a lower frequency. process (mclk) begin if mclk = '1' and mclk'event then clkdiv <= clkdiv + 1; end if; end process; cclk <= clkdiv(17); Hz

U1: x7seg port map( x(7 downto 0) => SW, x(15 downto 8) => fix, cclk => cclk, clr => clr, AtoG => AtoG, A => A); fix <= " ";-- left 2 digits = A5 end x7seg_test_arch;