VLSI Design Spring03 UCSC By Prof Scott Wakefield Final Project By Shaoming Ding Jun Hu

Our goal  The goal of the project is to design a high speed 3-tap Finite Impulse Response (FIR) filter using explicit arithmetic units instead of high level behavioral operations to speed-up the computation. The arithmetic units include a 48-bit adder and a 24-bit multiplier.

The structure of the FIR  Usual Implementation  Project Implementation

Multiplier  Standard multiplication

Multiplier  Booth’s algorithm (Radix-2)

Multiplier If Booth's recoded is +1, then set else if Booth's recoded is -1, then else Recoded a i a i-1 aiai … (0)

The implementation of multiplier in the project  Radix-4 Booth … (0) a i+1 aiai a i-1 Operation 000Add 0 x B 001Add +1 x B Add +2 x B 100Add -2 x B 101Add -1 x B Add 0 x B

The implementation of multiplier in the project  The Structure

Carry Save Adder (CSA) A B Carry In Sum //Sum and Carry comes out from CSA Carry Out Result //This uses propagate adder  Basic idea The basic idea is that three numbers can be reduced to 2, in a 3:2 compressor, by doing the addition while keeping the carries and the sum separate.

Carry Save Adder (CSA)  Wallace carry save adder tree  Full 3:2 compressor on k-bit-word.

48-bit Carry Look-ahead Adder

XOR

Final Results

Summary  The advantage of our structure Concurrent computation of each tap instead of the sequential one. Multiplier concurrent computation of partial products and summation using Wallace Tree via Carry-save Adder. Carry Look-ahead Adder in the final addition.  Conclusion Using arithmetic units (a 48-bit adder and a 24-bit multiplier.) instead of high level behavioral operations can highly speed-up the computation