Presentation to DØ STT Stony Brook by Reginald J. Perry, Ph.D. Professor and Chairman Department of Electrical and Computer Engineering (ECE) FAMU-FSU College of Engineering Florida A&M University Florida State University 1/28/2000 VHDL STATUS of CENTROID FINDER ALGORITHM

D0 STT Meeting at Stony Brook VHDL Status Background and Design Objective n Contacted in early December 1999 by Dr. Wahl. n Recruited two (2) new graduate students to work on project –Shweta Lolage – full-time GRA. –Kishma Meyers – part time –Roberto Brown - part time n Discussed initial algorithm with Eric Hazen just before Christmas 1999 –Working documents Earle, “A State Machine for Input of VTM Data to the Centroid Finder”, 7/20/99 Earle, “A Flowchart for the Centroid Finder”, 9/3/99 n Initial Design Objective –Complete baseline functional design by today’s meeting Conservative design, i.e. Ignore timing constraints No “Bells or Whistles”

D0 STT Meeting at Stony Brook VHDL Status Design Process n Altera FPLDs n Default Synthesis Settings n Partition Design into three parts –1. Decoder VTM FIFO Preprocessor FSM Centroid Finder FIFO –2. Buffer Filler Centroid Finder Algorithm minus “Calculator.” –3. Calculator Computes 13 bit centroid address

D0 STT Meeting at Stony Brook VHDL Status Block Diagram Decoder Buffer Filler Calculator Fifo data D1-D5 8 Vtm35 datatype pointer Fifo empty rdreqbusy datavalid

D0 STT Meeting at Stony Brook VHDL Status Decoder Block

D0 STT Meeting at Stony Brook VHDL Status Buffer Filler Block

D0 STT Meeting at Stony Brook VHDL Status Calculator Block

D0 STT Meeting at Stony Brook VHDL Status Functional Simulation Assumptions 1 MHz Clock Single Chip No Bad Channels No Skipped Channels

D0 STT Meeting at Stony Brook VHDL Status Sample Input Data and Expected Output Results

D0 STT Meeting at Stony Brook VHDL Status Functional Simulation

D0 STT Meeting at Stony Brook VHDL Status Resource Allocation Total logic cells used: 1433/2880 ( 49%) Total embedded cells used: 40/160 ( 25%) Total EABs used: 8/10 ( 80%) Average fan-in: 3.24/4 ( 81%) Total flipflops required: 481 Device EPF10K50EQC208-1

D0 STT Meeting at Stony Brook VHDL Status Current Status n Baseline Design Completed and Documented. n Static Timing Analysis of Baseline Design showed 30MHz Maximum Clock Freq –Performance limited by Buffer Filler Module. n Beginning Revision 2 Design based on Earle, et.al., “Specifications for the STC Daughtercard” –Add Hit Filter –Add 3 or 5 strip cluster finder option –Examine PCI bus interface –Add L3 buffer/monitoring requirements.