Verilog Module Module declaration Module instantiation module Add_full (sum, c_out, a, b, c_in); // parent module input a, b, c_in; output c_out, sum;

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Presentation transcript:

Verilog Module Module declaration Module instantiation module Add_full (sum, c_out, a, b, c_in); // parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Add_half M1 (w1, w2, a, b);// child module Add_half M2 (sum, w3, w1, c_in);// child module or (c_out, w2, w3);// primitive instantiation endmodule

Module Port Connections By position By name Empty port module child(a,b,c); … endmodule module parent; wire u,v,w; child m1 (u,v,w); child m2 (.c(w),.a(u),.b(v)); child m3 (u,,w); endmodule

Descriptive Styles Explicit structural description module Add_half (sum, c_out, a, b); inputa,b; outputsum, c_out; wirec_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule

module compare_2_str (A_lt_B, A_gt_B, A_eq_B, A0, A1, B0, B1); inputA0, A1, B0, B1; outputA_lt_B, A_gt_B, A_eq_B; wirew1, w2, w3, w4, w5, w6, w7; or(A_lt_B, w1, w2, w3); nor(A_gt_B, A_lt_B, A_eq_B); and(A_eq_B, w4, w5); and(w1, w6, B1); and(w2, w6, w7, B0); and(w3, w7, B0, B1); not(w6, A1); not(w7, A0); xnor(w4, A1, B1); xnor(w5, A0, B0); endmodule

Descriptive Styles Behavioral description module Flip_flop (q, data_in, clk, rst); input data_in, clk, rst; output q; reg q; (posedge clk) begin if (rst == 1) q = 0; else q = data_in; end endmodule

module compare_2_algo (A_lt_B, A_gt_B, A_eq_B, A, B); input[1:0]A, B; outputA_lt_B, A_gt_B, A_eq_B; regA_lt_B, A_gt_B, A_eq_B; (A or B)// Behavior and event expression begin A_lt_B = 0; A_gt_B = 0; A_eq_B = 0; if (A==B) A_eq_B = 1; else if (A > B) A_gt_B = 1; else A_lt_B = 1; end endmodule

Descriptive Styles Continuous Assignment module adder (a, b, sum, c_out); output sum, c_out; inputa, b; assign {c_out, sum} = a + b; endmodule

module compare_2ca (A_lt_B, A_gt_B, A_eq_B, A, B); input[1:0]A, B; outputA_lt_B, A_gt_B, A_eq_B; assign A_lt_B = (A < B); assign A_gt_B = (A > B); assign A_eq_B = (A == B); endmodule

Descriptive Styles Structural Predefined primitive Combinational circuits only User-defined primitive Instantiated modules Behavioral Continuous assignment Combinational circuits only Always construct Initial construct

Priority Encoder module PE (y0,y1,y2,y3, c0, c1); inputy0,y1,y2,y3; outputc0, c1; assign c0=y0|y1; assign c1=y0|(~y1 & y2); endmodule