הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות MidTerm Presentation Enhanced Ethernet Card Enhanced Ethernet Card Project num Students: Alex Shpiner Eyal Azran Supervisor: Boaz Mizrahi

Project’s goals:   Automatic ping reply   Real time Packet analyzer & data collector   Real time Network Testing Unit:   Predefined transmit rate   Accurate measurement of response time   Testing parameters are predefined by user

MACMAC CIFCIF TRN RCV ARB FPGA Architecture Shared bus TRP RCP * Configuration units (GNR, MCF) are not shown on this diagram

TRP – Transmit Processing Unit Echo Request Parameters Regular Packets to be transmitted Echo Request Generator Echo Reply Creator TRN Arbiter CIFCIF TRNTRN RCP TRP

Echo request parameters IPMAC Inter Packet Gap Total number of test cycles IP-MAC table:

Transmit Packets Buffer DATA FIFO TRANSMITTER EOP FIFO BE FIFO TRN_ARB TRN User Packets

Echo Request Creator DATA FIFO TRANSMITTER EOP FIFO BE FIFO TRN_ARB TRN Transmit Parameters Packet Creator

Echo Reply Creator DATA FIFO TRANSMITTER EOP FIFO BE FIFO TRN_ARB TRN Packet Creator RCP

TRN Arbiter

RCP – Receive Processing Unit Regular Packets Received Data Collector Packet Analyzer CIFCIF RCVRCV TRP RCP Echo RAM

RCP – Receive Processing Unit Data FIFO with Back Pointer Packet Received FSM AddressType TRP Echo received ERP ready Data Collector

IPMAC Min/Max Delay Total packages received Sources IP-MAC addresses table:

Approximated Time Table Time line Learning the Network Protocols Architecture Design and Algorithms Development Final Presentation and Project Book Submitting Writing the code and simulation Synthesis & Debug March 2004 April 2004 May to June 2004 Jule 2004 August 2004

Thanks