CSRD, University of Illinois at Urbana-Champaign 1 A Complete Compilation System

CSRD, University of Illinois at Urbana-Champaign 2 Conventional Approach Frontends –Parafrase-2 –Polaris –PFA –… Backends –MIPSPro FORTRAN –Visual C++ –GCC –... Compiler Frontend analysis & optimization Compiler Backend analysis & optimization Input Source Output Assembly Intermediate Code Lose Analysis Information!

CSRD, University of Illinois at Urbana-Champaign 3 NOW HUIRLUIRIUIR UMD F77 NUMA SMT EPIC SS C C++ Java Analysis Data, Control, Cost Symbolic, etc. Parallelization Loop and Functional Transformations Distribution, Fusion, Interchange, Unroll, etc. Standard Opt. Strength Reduct., CSE, CP, etc. Resource Allocation Machine Specific Optimizations Instruction Scheduling/ Packing ILP Opt. … Machine Indep. Peephole Opt. LUIR lowering Simplify to 3-addr code In-place to maintain analysis Opcode tagging Tag stmts w/ possible opcodes In place to maintain analysis The PROMIS ApproachPROMIS

CSRD, University of Illinois at Urbana-Champaign 4 The PROMIS HTG Acyclic Task Graph (at its core) –Single statement nodes –CFE, DDE, CDE Hierarchical Blocks –Loops become SESE compound nodes –HtgBBlock - may contain compound nodes Hierarchical Edges –Don’t cross levels of hierarchy Edges with higher levels source/sink into fake start/stop nodes Edges with lower levels source/sink into compound nodes

CSRD, University of Illinois at Urbana-Champaign 5 Block Start Stop HtgBBlock Start Stop Branch HtgBBlock Stop Start  HtgBBlock Loop CDE DDE CFE

CSRD, University of Illinois at Urbana-Champaign 6 Loop Start Stop HtgBBlock  Start Branch Stop i-assign p-add v-addri-var ia i-mult i-var cb a[i] = b + c

CSRD, University of Illinois at Urbana-Champaign 7 Retargeting PROMIS -- UMD All high and many low level optimizations and analyses operate on machine independent internal representation All machine specific information contained within the UMD description Code Generator and optimization parameters are retargeted simply by changing the UMD description

CSRD, University of Illinois at Urbana-Champaign 8 ??? NOW Multi- threaded Multi- proc Retargetable & Reconfigurable.c.cpp VLIW MD Vector Unit Instruction Scheduler Thread Unit Register Allocator Source files MD files PE MM MM M M Target

CSRD, University of Illinois at Urbana-Champaign 9 Information Provided by the UMD High Level –Types of parallelism available: multiprocessor, multithreading, vector units, etc. –Intrinsic function mappings Intermediate Level –Intrinsic function lowering Low Level –Opcode mapping, Instruction Formats, etc. –Resource usage, pipelines, latencies, etc.

CSRD, University of Illinois at Urbana-Champaign 10 Saving the PROMIS Internal Representation Can easily save and restore a program’s Internal Representation to a file Avoid re-executing the same passes on the same programs by saving intermediate results at the desired location More Comprehensive, less Destructive, and much Faster than generating C code NO analysis information is recomputed!

CSRD, University of Illinois at Urbana-Champaign 11 Common Uses: Repeated Experiments, Debugging Setup: Run initial passes and dump to file Use: Load from file and run experiment Run first N-1 Passes.PIR File Unload.PIR File Run experiment on (or debug) Pass N Load No need to repeat First N-1passes

CSRD, University of Illinois at Urbana-Champaign 12 Potential Uses Interface to connect PROMIS to other compilers, such as a back-end optimizer This interface is more expressive than dumping source code (e.g. can represent Data Dependence Analysis)

CSRD, University of Illinois at Urbana-Champaign 13 Main Issues Each class in the Internal Representation must implement Unload and Load functions Basic data types are written by value Objects are serialized and tokenized before being written to file