Computing Delay with Coupling Using Timed Automata Serdar Tasiran, Yuji Kukimoto, Robert K. Brayton Department of Electrical Engineering & Computer Sciences University of California, Berkeley,

Overview l A timed-automaton-based method for computing the delay of a combinational circuit. l Outline: u Why do we need a new method? u Timed automata s Representing sets of waveforms s Delay models s Hierarchical representation u The complexity problem s Hierarchical approach s Timed “image computation” s Heuristics u Status and Future Work

Why do we need a new method? From ICCAD ‘97 tutorial on timing analysis. (Devgan, et. al.) GOAL: Delay analysis tool that can handle ~100s of gates. l Must handle sophisticated delay models u Dynamic logic: Complex gates s Delay depends on relative arrival times and values of inputs. u Cross-talk between nodes, wires running parallel.

What about static analysis and simulation? Simulation l Number of possible input patterns exponential in # of inputs: è For large circuits, infeasible to simulate all patterns. l Delay not guaranteed unless all patterns are simulated. From ICCAD ‘97 tutorial on timing analysis. (Devgan, et. al.) Static Analysis l Topological delay does not account for cross-talk. l Assuming worst case cross-talk on all wires is too conservative.

OUR APPROACH l Timed automata serve as delay models for circuit components l Delay parameters obtained by u Simulation u Analytical methods l Formal timing verification used to compute delay u All patterns covered; delay guaranteed. From ICCAD ‘97 tutorial on timing analysis. (Devgan, et. al.)

Timed Automata l Clocks (timers): real-valued variables, increase at same rate. l For each location u an output assignment u an invariant: a clock predicate. Clock predicate: Positive Boolean combination of x  d and x   d. i o 2  delay  3 i = 1, x  0 i =0, x  3 o = 0 2  x  3 x  3 o = 0 o = 1 Initial 2 3 i o reset x

From ICCAD ‘97 tutorial on timing analysis. (Devgan, et. al.)

Timed Automata as Delay Models i =0, x  0 i =1, x  d fall,max Initial o = 1 i = 1, x  0 i = 0, x  d rise,max o = 0 x  d fall,max o = 1 o = 0 Initial x  d fall,max d fall,min  x x  d rise,max d rise,min  x x  d rise,max l Example: Inertial delay model for a wire segment. Determine d fall,min, d fall,max, d rise,min, d rise,max using simulation for various input patterns. l Construct timed automaton model with these parameters. l More sophisticated delay models can be expressed using timed automata. l Delay of this gate depends on u Old and new values of a, b, c, d, e u Relative arrival times of a, b, c, d, e l Modeling this circuit with [d min, d max ] is too coarse.

Modeling Cross-talk With Timed Automata l f and g are look-up tables  f increases x  wire k takes less time to rise  g decreases x  wire k takes longer to rise l f and g are determined by simulation or analytical computation and by conservative discretization. l Choosing a smaller time unit gives better accuracy but increases complexity. o k = 0, c k = risingo k = 0, c k = stable o k = 0, c k = rising o k = 1, c k = stable x  d rise,max d rise,min  x x  d rise,max d rise,min  x x  d rise,max d rise,min  x x  d rise,max i = 1 x  0 c j = rising x  f(x) c j = falling x  g(x) wire k aggressor wire j

Representing Sets of Input Waveforms l Two-vector delay: All inputs are initially stable and then switch simultaneously. clock = high i = i old i = i new For each input signal x  0 i = i old i = i new x = arrive i Different arrival times i = i old i = i new d min  x  d max Asynchronous input l Floating-mode: clock = high i = arbitrary i = i new For each input signal x  0

Composition of Timed Automata o p 3  delay  5 o= 0, y  0 o=1, y  5 p= 1 3  y  5 y  5 p= 1 p= 0 Initial B1B1 B3B3 B2B2 B i o 2  delay  3 A i = 0, x  0 i =1, x  3 o = 1 2  x  3 x  3 o = 1 o = 0 Initial A1A1 A3A3 A2A2 A || B i o p o=1, p=1 Initial (A 1, B 1 ) i = 0, x  0 i =1, x  3 o=1, p=1 (A 2, B 1 ) x  3 2  x  3 o=0, p=1 (A 3, B 2 ) y  5 y  0 3  y  5 o=0, p=0 (A 3, B 3 )

Variable Hiding (Smoothing) A||B i o p o=1, p=1 Initial (A 1, B 1 ) i = 0, x  0 i =1, x  3 o=1, p=1 (A 2, B 1 ) x  3 2  x  3 o=0, p=1 (A 3, B 2 ) y  5 y  0 3  y  5 o=0, p=0 (A 3, B 3 ) p=1 Initial (A 1, B 1 ) i = 0, x  0 i =1, x  3 p=1 (A 2, B 1 ) x  3 2  x  3 p=1 (A 3, B 2 ) y  5 y  0 3  y  5 p=0 (A 3, B 3 ) (  o) (A||B) i p

Hierarchical View of Circuits Higher Level Block = (  internal signals) ( Component 1 || Component 2 ||... Component n ) l “COMPOSE-SMOOTH” l To obtain simpler, smaller representation for HLB we often need to u Apply conservative abstraction, I.e., overapproximate behavior of product automaton.

Hierarchy Example XN = (  x, y, z) ( N 1 || N 2 || N 3 || N 4 ) l XN specifies exactly the set of possible waveforms at c for given a and b. l XN has 4 4 = 256 locations and 4 timer variables N4N4 N1N1 N2N2 N3N3 XN x y z a b c l Suppose the following representation is accurate enough l Can have timed automaton XN abstract with much fewer locations and one timer representing this information. l Pre-designed templates for abstraction áFormal guarantee that high level model is conservative. May be in transition d min,ab d max,ab Last transition of a or b c

Delay Computation with Timed Automata GIVEN l Set of primary input waveforms. u Represented by timed automaton I. l A combinational circuit u Described as an interconnection of components G 1, G 2, …, G k COMPUTE l The set of possible primary output waveforms  F = (  primary inputs, internal variables) ( I || G 1 || G 2 ||... || G k ) l Beautiful, but... u Problem: Complexity u Verification with timed automata is exponential in the number of timers. u State of the art: ~50 timers (KRONOS. Maler, et. al.) l We need the expressiveness and coverage of the timed automaton approach l Must find way to handle problem using max. ~50 timers at a time.

Hierarchy and Image Computation F G3G3 G5G5 G6G6 G4G4 I F = (  primary inputs, internal variables) ( I || G 1 || G 2 ||... || G k ) l Freedom in constructing evaluation tree l Has huge effect on the size of intermediate results l At each node of the tree, Can smooth variables occurring only in descendants of that node. l Evaluation tree corresponds to hierarchically partitioning the circuit. G2G2 G1G1

“Image Computation” cut-sets l Perform compositions in topological order. u Corresponds to propagating the set of primary input waveforms across the circuit. u Can smooth variables to the left of each cut set. l Conjecture: Can represent waveforms at each cut set using ~50 timers.

Compose-Smooth-Abstract l Key subroutine for this approach. ALGORITHM: l Take product of component automata l Smooth internal variables l Perform “untimed reachability analysis” on product automaton u Ignore timing information on edges u Perform reachability analysis considering logical functionality only u Conservative: Less minimization than timed analysis. u BUT efficient: Complexity does not depend on timers. l Apply timer minimization algorithm of [Daws, Yovine, RTSS ‘96]. Identifies: u Timers that can’t be simultaneously active u Timers that have equal values u Important observation: Only the # of simultaneously active, unique timers affects complexity. u Conjecture: For shallow DSM circuits, few timers should be required.

Other Heuristics BISIMILARITY MINIMIZATION l Smoothing internal variables results in many silent transitions l Likely to have many bisimilar locations. l Perform bisimilarity minimization on automaton, treating resets and timer predicates as untimed symbols. u Sufficient check for timed bisimilarity u Efficient: No exponential dependency on timers. PARTITIONING l Partitions with disjoint support u Can smooth inputs to partition l Partitions with few output variables u Smaller automata u Identify “bottle-necks” in topology l Long and narrow partitions l Apply “SMOOTH-ABSTRACT” when intermediate results get large. l Divide sets of waveforms into separate sets.

Advantages of Approach l Modeling issues and verification and analysis issues are decoupled. l Timed automata serve as clean interface between the two. l The same algorithms remain applicable u For different delay models u At different levels of the hierarchy l Efficiency can be traded-off for accuracy without modifying analysis algorithm. l Precise, exact characterization of delay computation problem u Allows sound conservative simplifications. l Timing properties other than delay can be verified u Hold and set-up times u For dynamic logic, is the input pulse wide enough to discharge output? u Is there a channel-connected path from supply to ground? l Flexibility in clustering and image computation u Room for heuristics.

Status and Future Work l Timed-automaton-based delay computation algorithm implemented inside MOCHA. u BDD based implementation u Makes use of VIS model checker u Works on flat representation only l Will implement u Timer minimization algorithm u Abstraction templates u Algorithm computing bisimilarity quotient u Partitioning heuristics l Experience from asynchronous circuits: u With carefully chosen abstractions, was able to handle circuit with ~100 gates l We hope to achieve the same for combinational circuits.

3 Claims Made in This Talk l Timed automata make good DSM delay models. l They decouple modeling and analysis issues, and enable exact formalization of problem. l Using hierarchy, abstraction and heuristics, the computational issues can be overcome.