Pulse Generator High Speed Digital Systems Lab Winter 2007/08 Design Presentation (Midterm ) Instructor: Yossi Hipsh Students: Lior Shkolnitsky, Yevgeniy Lobanov

2 Topics Review Review Block Diagram Block Diagram Bill Of Materials Bill Of Materials Electrical Scheme Electrical Scheme Layout Stack Layout Stack Future Plans – Time Table Future Plans – Time Table

3 Review The main goal is to build a Programmable Pulse Generator. The main goal is to build a Programmable Pulse Generator. The Generator will be integrated into an existing lab experiment, that teaches about High Speed Systems Phenomena: reflections, skew and jitter. The Generator will be integrated into an existing lab experiment, that teaches about High Speed Systems Phenomena: reflections, skew and jitter. The Generator will create a very short (0.5-1 nsec) and a longer (10-13 nsec) pulse signal into transmission line. The Generator will create a very short (0.5-1 nsec) and a longer (10-13 nsec) pulse signal into transmission line.

4 I/O scheme Programmable Pulse Generator Power supply Pulse width selection Short pulse Long pulse

5 Detailed Block Diagram Detailed Block Diagram Splitter Oscillator AND Manual Selector Programmable Delay Programmable Delay Voltage Regulator FF Voltage Regulator Power Supply 9 V Level Translator TTL Diff LVPECL 5 V 3.3 V 100 nsec 10 nsec nsec 3.3 V 2.3 V nsec

BOM NamePart NumberQnt.Exists 1Voltage Regulator LM1085 – 5V1Yes LM1085 – 3.3V1Yes LM1085 – ADJ1Yes 210MHz Oscillator CO10251Yes 3Flip Flop MC74F74N1Yes 4TTL to LV PECL Translator MC100EPT201No 5Splitter (Fan Out Buffer) MC100EP111No 6Programmable Delay MC10EP1952No 7AND Gate MC10EP051No 8Manual Selector DIP 54Yes 9Resistors ---Yes 10Capacitors--- Yes Appendix 1 (click to jump)

Electrical Scheme

Layout Stack SIGNAL FR 4 GND Vcc (ECL) = 3.3 V Vtt = 1.3 V Vcc (TTL) = 5 V FR 4 each metal layer - 1oz Copper each dielectric layer - TBD

Future Plans – Time Table End date 24/131/17/214/223/2 Making the board Building the prototype The test setup – designing, debugging Writing the report Final Presentation

10 Questions / Answers Thank you!

11 Appendix 1 Resistance [Ω]quantity ResistorsCapacitors Capacitance [μF]quantity Go back…

Electrical Scheme (Signal Path Only)

Time Table Task \ Week Exploring the problem Definition presentation Block diagram consolidation Finding suitable components Designing the board Design presentation Ordering components and board Writing the booklet Designing a test setup Building the project Building the test setup Test and Debug Final presentation

100 nsec 10 nsec nsec 3.3 V 2.3 V nsec