Tera-Pixel APS for CALICE Progress meeting, 17 th May 2006 Jamie Crooks, Microelectronics/RAL.

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Presentation transcript:

Tera-Pixel APS for CALICE Progress meeting, 17 th May 2006 Jamie Crooks, Microelectronics/RAL

Bump Bonding Gold stud + conductive glue 100um pads (may be able to bump to standard pad cells) Heat (>175 o ) + Pressure Hand alignment & trials  extra effort req’d Physical size may be problematic –2inch hotplate –Would eventually need very large cavity reflow oven Indium requires special wafer processing

Centralised controller Fully Independent pixels Centralised memory + controller TimeCodes HitData TimeCodes, Control signals HitData TimeCodes KeyActive Control logicMemory cellsPixels containing diodes Control signals -DRAMs only  max 4 regs per pixel -Most regs not used -Time code & data sense circuits required for every column (N) -Control logic complex  large area -Significant dead space in every pixel  poor charge collection -DRAMs only  max 4 regs per pixel -Time code & data sense circuits required for every column (N) +Complex control logic moved out of pixel -Reduced dead space in every pixel  better charge collection -Dead area ~6% -SRAMs can be used in dead areas -Limited storage facility (calc overflow prob!) -Only 1-in-N time code & data sense circuits +Complex control logic moved out of pixel -Reduced dead space in every pixel  better charge collection -Dead area ~6% Three Alternative Architectures See separate PowerPoint

Analog Sum “Operating point” Vout bias

Analog Sum 450 electrons 1 diode collects all Sweep diode reset point

Analog Sum 450 electrons 1 diode collects 450e 2 diodes collect 225e 3 diodes collect 150e 4 diodes collect 112e Sweep diode reset point

Analog Sum 450 electrons 4 diodes collect 112e Sweep diode reset point 4 cases: bias currents 250nA 500nA 750nA 1uA