CS 61C L25 VM III (1) Garcia, Spring 2004 © UCB TA Chema González www-inst.eecs/~cs61c-td inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 25 –VM III Netsky/Bagle/MyDoom War "Hey, Netsky...don't ruine (sp) our bussiness (sp), wanna start a war?" [Bagle.J worm's code]

CS 61C L25 VM III (2) Garcia, Spring 2004 © UCB Review… Manage memory to disk? Treat as cache Included protection as bonus, now critical Use Page Table of mappings for each user vs. tag/data in cache TLB is cache of Page Table Virtual Memory allows protected sharing of memory between processes Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well

CS 61C L25 VM III (3) Garcia, Spring 2004 © UCB Locality… Spatial Locality != Temporal Locality SL: If I access X, I’ll (probably) stay close TL: If I access X, I’ll (probably) get back soon Normally both hold, but… Sequential memory access: SL, not TL Lab8 experiment, large stride: TL, not SL

CS 61C L25 VM III (4) Garcia, Spring 2004 © UCB Peer Instructions A. Locality is important yet different for cache and virtual memory (VM): temporal locality for caches but spatial locality for VM B. Cache management is done by hardware (HW), page table management by the operating system (OS), but TLB management is either by HW or OS C. VM helps both with security and cost ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS 61C L25 VM III (5) Garcia, Spring 2004 © UCB Peer Instruction 1. Locality is important yet different for cache and virtual memory (VM): temporal locality for caches but spatial locality for VM 2. Cache management is done by hardware (HW), page table management by the operating system (OS), but TLB management is either by HW or OS 3. VM helps both with security and cost T R U E F A L S E 1. No. Both for VM and cache 2. Yes. TLB SW (MIPS) or HW ($ HW, Page table OS) 3. Yes. Protection and a bit smaller memory T R U E ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

CS 61C L25 VM III (6) Garcia, Spring 2004 © UCB Virtual Memory Problem #1 Slow: Every memory access requires: -1 access to PT to get VPN->PPN translation -1 access to MEM to get data at PA Solution: Cache the Page Table -Make common case fast -PT cache called “TLB” “block size” is just 1 VA->PA mapping TLB associativity?

CS 61C L25 VM III (7) Garcia, Spring 2004 © UCB Virtual Memory Problem #2 Page Table too big! 4GB Virtual Memory ÷ 1 KB page  ~ 4 million Page Table Entries  16 MB just for Page Table for 1 process, 8 processes  256 MB for Page Tables! Spatial Locality to the rescue Each page is 4 KB, lots of nearby references But large page size wastes resources No matter how big program is, at any time only accessing a few pages “Working Set”: recently used pages

CS 61C L25 VM III (8) Garcia, Spring 2004 © UCB Solutions Page the Page Table itself! Works, but must be careful with never- ending page faults Pin some PT pages to memory 2-level page table Solutions tradeoff in-memory PT size for slower TLB miss Make TLB large enough, highly associative so rarely miss on address translation CS 162 will go over more options and in greater depth

CS 61C L25 VM III (9) Garcia, Spring 2004 © UCB 2-level Page Table 0 Physical Memory 64 MB Virtual Memory  Code Static Heap Stack nd Level Page Tables Super Page Table

CS 61C L25 VM III (10) Garcia, Spring 2004 © UCB Page Table Shrink : Single Page Table Page Number Offset 20 bits12 bits Multilevel Page Table Page NumberSuper Page No. Offset 10 bits 12 bits Only have second level page table for valid entries of super level page table Exercise 7.35 explores exact space savings

CS 61C L25 VM III (11) Garcia, Spring 2004 © UCB Three Advantages of Virtual Memory 1) Translation: Program can be given consistent view of memory, even though physical memory is scrambled (illusion of contiguous memory) All programs starting at same set address Illusion of ~ infinite memory (2 32 or 2 64 bytes) Makes multiple processes reasonable Only the most important part of program (“Working Set”) must be in physical memory Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later

CS 61C L25 VM III (12) Garcia, Spring 2004 © UCB Three Advantages of Virtual Memory User program view of memory: Contiguous Start from some set address Infinitely large Is the only running program Reality: Non-contiguous Start wherever available memory is Finite size Many programs running at a time

CS 61C L25 VM III (13) Garcia, Spring 2004 © UCB Three Advantages of Virtual Memory 2) Protection: Different processes protected from each other Different pages can be given special behavior - (Read Only, Invisible to user programs, etc). Kernel data protected from User programs Very important for protection from malicious programs Special Mode in processor (“Kernel more”) allows processor to change page table/TLB 3) Sharing: Can map same physical page to multiple users (“Shared memory”)

CS 61C L25 VM III (14) Garcia, Spring 2004 © UCB Virtual Memory Overview Let’s say we’re fetching some data: Check TLB (input: VPN, output: PPN) -hit: fetch translation -miss: check page table (in memory) –page table hit: fetch translation –page table miss: page fault, fetch page from disk to memory, return translation to TLB Check cache (input: PPN, output: data) -hit: return value -miss: fetch value from memory

CS 61C L25 VM III (15) Garcia, Spring 2004 © UCB A: A: 1 2 TRUE B: B: 1 3 TRUE C: C: 2 3 TRUE D: D: 1 TRUE E: E: 2 TRUE F: F: ALL FALSE Peer Instruction 1. Increasing at least one of {associativity, block size} is always a win 2. Higher DRAM bandwidth translates to a lower miss rate 3. DRAM access time improves roughly as fast as density

CS 61C L25 VM III (16) Garcia, Spring 2004 © UCB A: A: 1 2 TRUE B: B: 1 3 TRUE C: C: 2 3 TRUE D: D: 1 TRUE E: E: 2 TRUE F: F: ALL FALSE Peer Instruction Answers 1. Increasing at least one of {associativity, block size} is always a win 2. Higher DRAM bandwidth translates to a lower miss rate 3. DRAM access time improves roughly as fast as density F A L S E 1. Assoc. may increase access time, block may increase miss penalty 2. No, a lower miss penalty 3. No, access = 9%/year, but density = 2x every 2 yrs! F A L S E

CS 61C L25 VM III (17) Garcia, Spring 2004 © UCB Address Translation & 3 Concept tests PPNOffset Physical Address VPNOffset Virtual Address INDEX TLB Physical Page Number P. P. N.... V. P. N. Virtual Page Number V. P. N. TAGOffsetINDEX Data Cache Tag Data

CS 61C L25 VM III (18) Garcia, Spring 2004 © UCB Peer Instruction (1/3) 40-bit virtual address, 16 KB page 36-bit physical address Number of bits in Virtual Page Number/ Page offset, Physical Page Number/Page offset? Page Offset (? bits)Virtual Page Number (? bits) Page Offset (? bits)Physical Page Number (? bits) A: A: 22/18 (VPN/PO), 22/14 (PPN/PO) B: B: 24/16, 20/16 C: C: 26/14, 22/14 D: D: 26/14, 26/10 E: E: 28/12, 24/12

CS 61C L25 VM III (19) Garcia, Spring 2004 © UCB Peer Instruction (1/3) Answer 40-bit virtual address, 16 KB (2 14 B) 36-bit physical address, 16 KB (2 14 B) Number of bits in Virtual Page Number/ Page offset, Physical Page Number/Page offset? Page Offset (14 bits)Virtual Page Number (26 bits) Page Offset (14 bits)Physical Page Number (22 bits) A: A: 22/18 (VPN/PO), 22/14 (PPN/PO) B: B: 24/16, 20/16 C: C: 26/14, 22/14 D: D: 26/14, 26/10 E: E: 28/12, 24/12

CS 61C L25 VM III (20) Garcia, Spring 2004 © UCB Peer Instruction (2/3): 40b VA, 36b PA 2-way set-assoc. TLB, 256 entries, 40b VA: TLB Entry: Valid bit, Dirty bit, Access Control (say 2 bits), Virtual Page Number, Physical Page Number Number of bits in TLB Tag / Index / Entry? Page Offset (14 bits)TLB Index (? bits)TLB Tag (? bits) VD Access (2 bits)Physical Page No. (? bits) A: A: 12 / 14 / 38 (TLB Tag / Index / Entry) B: B: 14 / 12 / 40 C: C: 19 / 7 / 45 D: D: 19 / 7 / 58

CS 61C L25 VM III (21) Garcia, Spring 2004 © UCB A: A: 12 / 14 / 38 (TLB Tag / Index / Entry) B: B: 14 / 12 / 40 C: C: 18 / 8 / 45 D: D: 18 / 8 / 58 Peer Instruction (2/3) Answer 2-way set-assoc data cache, 256 (2 8 ) entries, 2 entries per set => 2 7 sets (7-bit index) Data Cache Entry: Valid bit, Dirty bit, Access Control (2 bits?), Virtual Page Number, Physical Page Number Page Offset (14 bits) Virtual Page Number (26 bits) TLB Index (7 bits)TLB Tag (19 bits) VD Access (2 bits)Physical Page No. (22 bits)

CS 61C L25 VM III (22) Garcia, Spring 2004 © UCB Peer Instruction (3/3) 2-way set-assoc, 64KB data cache, 64B block Data Cache Entry: Valid bit, Dirty bit, Cache tag + ? bits of Data Number of bits in Data cache Tag / Index / Offset / Entry? Block Offset (? bits) Physical Page Address (36 bits) Cache Index (? bits)Cache Tag (? bits) VD Cache Data (? bits) A: A: 12 / 9 / 14 / 87 (Tag/Index/Offset/Entry) B: B: 20 / 10 / 6 / 86 C: C: 20 / 10 / 6 / 534 D: D: 21 / 9 / 6 / 87 E: E: 21 / 9 / 6 / 535

CS 61C L25 VM III (23) Garcia, Spring 2004 © UCB Peer Instruction (3/3) Answer 64 KB / 64 B = 1K blocks, 2-way set-assoc data cache => 1K / 2 = 512 sets (9 bit index) Data Cache Entry: Valid bit, Dirty bit, Cache tag + 64 Bytes of Data Block Offset (6 bits) Physical Page Address (36 bits) Cache Index (9 bits)Cache Tag (21 bits) VD Cache Data (64 Bytes/ 512 bits) A: A: 12 / 9 / 14 / 87 (Tag/Index/Offset/Entry) B: B: 20 / 10 / 6 / 86 C: C: 20 / 10 / 6 / 534 D: D: 21 / 9 / 6 / 87 E: E: 21 / 9 / 6 / 535

CS 61C L25 VM III (24) Garcia, Spring 2004 © UCB $&VM Review: 4 Qs for any Mem. Hierarchy Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? (Write strategy)

CS 61C L25 VM III (25) Garcia, Spring 2004 © UCB Block 12 placed in 8 block cache: Fully associative, direct mapped, 2-way set associative S.A. Mapping = Block Number Mod Number Sets Block no. Fully associative: block 12 can go anywhere Block no. Direct mapped: block 12 can go only into block 4 (12 mod 8) Block no. Set associative: block 12 can go anywhere in set 0 (12 mod 4) Set 0 Set 1 Set 2 Set Block-frame address Block no. Q1: Where block placed in upper level?

CS 61C L25 VM III (26) Garcia, Spring 2004 © UCB Direct indexing (using index and block offset), tag compares, or combination Increasing associativity shrinks index, expands tag Block offset Block Address Tag Index Q2: How is a block found in upper level? Set Select Data Select

CS 61C L25 VM III (27) Garcia, Spring 2004 © UCB Easy for Direct Mapped Set Associative or Fully Associative: Random LRU (Least Recently Used) Miss Rates Associativity:2-way 4-way 8-way SizeLRU Ran LRU Ran LRU Ran 16 KB5.2%5.7% 4.7%5.3% 4.4%5.0% 64 KB1.9%2.0% 1.5%1.7% 1.4%1.5% 256 KB1.15%1.17% 1.13% 1.13% 1.12% 1.12% Q3: Which block replaced on a miss?

CS 61C L25 VM III (28) Garcia, Spring 2004 © UCB Q4: What to do on a write hit? Write-through update the word in cache block and corresponding word in memory Write-back update word in cache block allow memory word to be “stale” => add ‘dirty’ bit to each line indicating that memory be updated when block is replaced => OS flushes cache before I/O !!! Performance trade-offs? WT: read misses cannot result in writes WB: no writes of repeated writes

CS 61C L25 VM III (29) Garcia, Spring 2004 © UCB In Conclusion… Virtual memory to Physical Memory Translation too slow? Add a cache of Virtual to Physical Address Translations, called a TLB Need more compact representation to reduce memory size cost of simple 1-level page table (especially 32-  64-bit address) Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well Virtual Memory allows protected sharing of memory between processes with less swapping to disk