Synthesis For Mixed CMOS/PTL Logic

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Presentation transcript:

Synthesis For Mixed CMOS/PTL Logic DATE-200 - CMOS/PTL 4/17/2017 Synthesis For Mixed CMOS/PTL Logic Congguang Yang Maciej Ciesielski cyang@synopsys.com ciesiel@ecs.umass.edu Dept. of Electrical & Computer Engineering University of Massachusetts Amherst, MA 01003 / USA

BDD-based Logic Decomposition DATE-200 - CMOS/PTL 4/17/2017 BDD-based Logic Decomposition Observation: BDD structure reveals functional decomposition. Identify dominators 1-dominator – algebraic AND 0-dominator – algebraic OR x-dominator – algebraic XOR Generalized dominator Boolean AND/OR Generalized x-dominator Boolean XNOR Cofactor wrt single node simple MUX Cofactor wrt super node complex MUX 2

Boolean AND/OR Decomposition using generalized dominator DATE-200 - CMOS/PTL 4/17/2017 Boolean AND/OR Decomposition using generalized dominator Find a cut in BDD of F Create divisor D (generalized dominator) Compute Q from F use don’t care of OFF(D) for conjunctive decomp. Compute R from F use don’t care of ON(D) for disjunctive decomp. Minimize Q (R) with DC

Conjunctive Boolean decomposition - example DATE-200 - CMOS/PTL 4/17/2017 Conjunctive Boolean decomposition - example F = D Q g d e a f b c F 1 reduce D = af + b + c a f b c D 1 a f b c D 1 g d e a f b c Q 1 DC minimize g d e a Q 1 Q = ag + d + e

Previous work on BDD decomposition [Karplus 1988] DATE-200 - CMOS/PTL 4/17/2017 Previous work on BDD decomposition [Karplus 1988] F a b c d 1 d 1 c a b * a + b c + d 1-dominator Special cases of a generalized dominator a b c d 1 F a b 1 d c a b c d 0-dominator

XOR Decomposition – role of x-dominator DATE-200 - CMOS/PTL 4/17/2017 XOR Decomposition – role of x-dominator General idea: Identify a node (x-dominator) with complement and regular edges Split node function into f and f’ Compose the two parts with XOR

MUX Decomposition 1 v h g f g f F 1 Simple MUX Complex MUX DATE-200 - CMOS/PTL MUX Decomposition 4/17/2017 F h f g 1 F v f g 1 Simple MUX Complex MUX Identify exactly two nodes covering all paths to 1, 0 Connect one node to 1, the other to 0 Upper portion defines control h 1 b a F d c

Decomposition of multiple-output functions DATE-200 - CMOS/PTL 4/17/2017 Decomposition of multiple-output functions Build BDD for each output Decompose each BDD Construct factoring trees Identify logic sharing

Application to CMOS/PTL logic synthesis DATE-200 - CMOS/PTL 4/17/2017 Application to CMOS/PTL logic synthesis Logic balancing Reducing long transistor chains Fanout reduction

Application to CMOS/PTL logic synthesis DATE-200 - CMOS/PTL 4/17/2017 Application to CMOS/PTL logic synthesis Extract XOR’s and MUXes during BDD decomposition Map the decomposed logic onto CMOS and PTL Preserve XOR’s and MUXes for PTL Use CMOS to provide buffering for PTL New technology mapping techniques needed (tree-based mappers are inadequate) Develop PTL cell library (with and w/out buffers)

Preliminary Results – XOR intensive logic DATE-200 - CMOS/PTL 4/17/2017 Preliminary Results – XOR intensive logic Comparison with SIS and [Tsai’96] # XOR’s: after/before technology mapping SIS mapper used (lower cost assigned to XOR gates)