Fiber Channel Video Controller Students: Tsachy Kapchitz Michael Grinkrug Supervisor: Alex Gurovich in cooperation with: Elbit Systems המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

FC supports both Channel (SCSI etc.) and Network (TCPIP etc.) protocols high frequency (few Gb/s) over serial link - optical or copper FC Frame Header

For Elbit Systems Ltd. Video data has to be delivered fast and reliably from the camera to the monitor, including additional information describing the current picture. FC network may contain many different devices, so destination and other parameters have to be checked. In order to simplify the overall system, a controller will “listen” to the FC network and send only the relevant pictures to the monitor using appropriate video system settings. All the required protocol processing will be done by the hardware. One of the standards, supported by FC is AV - Fiber Channel Audio Visual protocol. It defines the ways to use FC for real-time video transmission using mostly hardware and minimal software.

FC Receiver by HP® FC-AV Controller Monitor Driver Unit FC network Monitor Design a controller that supports: FC frame header processing AV container system processing and: Grabs the frames directed to it Processes the headers Keeps track of video containers Writes ancillary data into memory Extracts video fields to a monitor Project Goal

General Block Diagram Container Header processing Fiber Channel Frame Header processing Configuration and Status report Video Pixels output to the monitor

Testing Methodology Generate Test file VHDL model Check output files Correct ? yesyes Save the failed test for manual check no Testing is done using an input test file, generated by a C program using maximum possible randomization in order to get full coverage. VHDL test-bench feeds the data into the controller’s model. Output data is compared to the expected output file. The whole testing process is automated, using the VHDL simulator in a batch mode and running the above process in a loop. After the simulation testing is finished, the design is tested on a board by Gidel Ltd. using Altera’s Apex20K FPGA chip.