Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logic Gates: NOT a Prerequisite! Today: Gates, gates and more gates What each gate does Combining gates to perform a function Gate Delays: A result of capacitance and resistance Prerequisite: Know what binary numbers are

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logic Gates -- From Lecture 1 A B C=A·B AND C = A B NAND NOR A B NOT A OR A B C=A+B EXCLUSIVE OR A B

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logic Gates – How are they used? A B C=A·B AND What does it mean to put 1’s and 0’s through this gate? C would have the value of 1.5 V (logical 1). But it would have the value of 0V logical 0 if either one of the inputs were held at zero V. AND 1.5V Suppose 1.5 V is logical 1 and 0V is logical 0. “Ground”

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California How to Combine Gates to Produce a Logic Function? (Logical Synthesis) Not-AND = NAND A B A B NOT AND Logically just an AND plus a NOT gate: Example A B AND Shorthand for NOT

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California The Most Common Functions/Gates ABAB Not-AND = NAND A B AB A+B BA Not-OR = NOR A B Typically use one or the other: “NAND logic” or “NOR logic” Truth Table

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logical Synthesis A Example F= A B. B A B A B. Shorthand:

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logical Synthesis Suppose we are given a truth table—that is, a list of the output we want for every possible combo of inputs. Is there a method to implement the logical function? Answer: There are lots of ways, but one simple way is implementation from “sum of products” formulation. How to do this: 1) Write sum of products expression from truth table and 2) Implement using standard gates. (Warning this is probably inefficient – we need to minimize, or simplify the expression)

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logical Synthesis Example: ABCF or Clearly: F= 1 if C = 1 AB =1 i.e. F= C +AB Look at where function is “1”. Write product of A, B, C that makes it “1”. Do this for each “1” in the function, sum up.

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logical Synthesis Example: ABCF F= C +AB A B C A B C F

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California More Logical Synthesis Example: ABF F=A +AB A B A B F Clearly Thus But it is easy to show that a simpler valid expression for F is F = B, hence: B F

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Logical Synthesis Guided by DeMorgan’s Theorem DeMorgan’s Theorem : or Thus, for example: A B C D F Thus any sum of products expression can be synthesized from NAND gates alone!

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Limitations of Digital Systems Sum of products uses large number of gates—more stages can simplify Complex systems have many, many stages of functions The longer the path of the voltage signal, the more noise it picks up: “pulse degradation” Physical properties of gates, resistance and capacitance, delay response “gate delay”

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California PHYSICAL LIMITATIONS OF LOGIC GATES Computer Datapath: Connected logic gates C D Thus, output of all circuits, including logic gates is delayed from the input. In Lecture 4 we will look into such delays quantitatively. A B Every node in any circuit (such as the internal circuit of a NAND gate) has capacitance and all interconnects have resistance. Thus it takes time to charge these capacitances.

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California UNIT GATE DELAY  D Time delay  D occurs between input and output: “computation” is not instantaneous Value of input at t = 0 + determines value of output at later time t =  D A B C Logic State t t DD 0 0 Input (A and B tied together) Output

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California Synchronous and Asynchronous Logic Time delay occurs between input and output in real logic circuits. Therefore the time at which output appears is difficult to predict… it depends for example on how many gates you go through. A B C In the “clocked” NAND gate above, the values of A and B are allowed through the gate only when the clock signal K is turned on. We use the clock signal to make the computation wait until A and B, which are possibly outputs from other functions, reach their stable values. K To make logic operations as fast as possible, we need predictability of signal availability. That is we want to know exactly when “C” is correctly computed from A and B. This requirement argues for synchronous logic, in which a clock signal actually initiates the computation of C. We will not distinguish asynchronous vs synchronous logic for the moment.

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California EFFECT OF GATE DELAY Cascade of Logic Gates A B C D Inputs have different delays, but we ascribe a single worst-case delay  to every gate How many “gate delays for shortest path? ANSWER : 2 How many gate delays for longest path?ANSWER : 3

Sheila Ross and W. G. OldhamEECS 40 Fall 2002 Lecture 2 Copyright Regents of University of California D t t t t t Logic state    22 22 0 33  TIMING DIAGRAMS Show transitions of variables vs time A B C Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. Note becomes valid one gate delay after B switches 1 0 The final OR gate creates one more delay.