Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 1 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Part 5 Fundamentals in Computer Design Computer Architecture Slide Sets WS 2011/2012 Prof. Dr. Uwe Brinkschulte Prof. Dr. Klaus Waldschmidt

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 2 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A hierarchy of definitions A computer realizes with all his components a complete Hardware-Software-System. The hierarchy of definitions of the system architecture can be expressed by a tree structure. System Architecture Hardware System Architecture (HSA) Software System Architecture (SSA) Computer Technology Computer Architecture # processor # memory # bus Microarchitecture functional units (ALU), register, caches, control unit, etc. Processor Architecture, Instruction Set Architecture (ISA) instruction set register file addressing modes Computer Organization, Macroarchitecture

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 3 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hardware System Architecture - HSA The hardware system architecture (HSA) describes the organization and architecture of the computer and defines the hardware components for implementation. The computer organization is partitioned in two levels: macro level micro level At the macro level the global structure of the computer is defined. The micro level instead describes the inner structure and implementation of the data path components, the busses, the caches, control unit etc. The instruction set architecture (ISA) is regarded as part of the computer architecture. The ISA describes the instruction set, the addressing modes and models the register file. It is an abstract interface between the software and hardware part of the computer. Software System Architecture High Level Language Compiler Assembler Instruction Set architecture (ISA) Hardware System Architecture Organization Microarchitecture

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 4 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Instruction Set Architecture RISC / CISC Instruction Set Architectures can be partitioned in:  RISC: Reduced Instruction Set Computer and  CISC: Complex Instruction Set Computer In modern microprocessors both paradigms are used more and more in combination.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 5 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt RISC-ISA A RISC-ISA consists of a simple structured instruction set, a comparable small number of different instructions, some few and simple addressing modes and a large register set. The instructions work on the internal registers only except some special load/store instructions to exchange register content with memory (Load-/Store-Architecture) The advantage of a simple instruction set is a high execution speed, efficient use of pipelining and an efficient decoding. Decoding is realized by a hardwired control unit Example: SUN SPARC instruction set

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 6 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt RISC-ISA The disadvantage of the RISC-ISA is the high semantic gap between the High Level Language (HLL) and the simple assembler instructions. This high semantic gap has to be bridged by the compiler. Therefore the compiler is of high importance in the transformation from HLL to assembler in a RISC architecture. The length of the code increases as the instruction set of the computer become simpler. HLL- program Compiler Assembler control information Decoding by hardwired control unit

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 7 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt CISC-ISA A CISC-ISA has a complex instruction set with a high number of different instructions (opcodes) and a lot of sophisticated addressing modes. All instructions can operate on registers or memory The CISC instruction set supports directly the constructs of a high level language. The compilation process is much easier and the length of the code become shorter, compared to a RISC instruction set. A very well-known CISC-ISA is the instruction set of the X86 family.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 8 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt CISC-ISA The main disadvantage of a CISC- ISA is a reduced execution speed, because of an inefficient use pipelining. The decoding is a very complex task and has to be solved by a micro programmed control unit. Microprogramming is of great importance in a CISC architecture. HLL- program Compiler Assembler control information micro programmed decoding (micro programmed control unit) Microcode

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 9 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt ISA on today‘s processors To combine advantages of RISC ands CISC ISA, today’s processor use a two level approach: Example: Intel Pentium II, III, 4 (x86 CISC instruction set, internal RISC architecture) CISC ISA RISC ISA Predecoder, Instruction Sequencer RISC Microarchitecture Processor

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 10 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Tuple model for the design of a computer architecture The principle of operation (functionality or behavior), the structure (digital circuits) and the chip integration (VLSI - Implementation) defines a model for designing a computer architecture. CA = (B, S, C) B = Behavior S = Structure C = Chip The three domains of the tuple together with some levels of abstraction are structured in the well-known Gajski/Kuhn-Diagram. For the design of a processor or a complete embedded system, all domains and levels of the Gajski/Kuhn-diagram have to be considered. Today, nearly all transformations starting from the system specification are supported and automated by software tools.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 11 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Views (domains) and levels of abstraction in the Y-Diagram of Gajski/Kuhn System level Geometry (Chip) Behavior Structure Algorithm level Register Transfer level Logic level circuit level CPU, Memory Processor, Subsystem Module: ALU, Register, MUX Logic, Flip-flop Transistor Mask/ Polygon level cell level Macrocell level Floor plan level Chip level System- specification Algorithm Register-Transfer Model Boolean Function Differential Equation

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 12 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 13 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Design of heterogeneous, embedded systems Processors or complete computer systems are more and more integrated in application systems. The computer, which realizes a Hardware/Software System (HW/SW), becomes “embedded” in the technical system. A computer designed to control such a technical environment is called Embedded System Digital HW Analog HW Mechanics, Operating system Hydraulics, … Software Technical environment like

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 14 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Design of heterogeneous, embedded systems The design of such heterogeneous systems is a very complex task, because a lot of different models, descriptions and paradigms have to considered. The main procedure for the design of of embedded systems is the refinement from specification to implementation and the verification under the V-Model. Digital HW Analog HW Mechanics, Operating system Hydraulics, … Software Technical environment like

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 15 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Modeling Simulation Validation Verification Hardware Architecture IP Reuse ( Platform Design) Simulation Refinement Synthesis Silicon Technology Integrated Circuit CMOS System Specification Design levels from the hardware point-of-view

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 16 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Design transformation steps For demonstrating the complexity of transformations in the design process, the transformation from the executable specification to the executable register transfer model is presented. Executable specification Functional model Timed functional model Transaction specified model Cycle based register transfer model parallelism delays (predicted) busses, communication cycles

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 17 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt The V-model of the design process The V model is a standard design model. The main procedure within the V-model is the refinement process. This refinement process means a stepwise -mostly interactive- transformation between levels of abstraction and views or domains of the Gajski-Diagram. The transformation steps are very complex tasks and mainly supported by software tools. One axis of the V defines the implementation and the other one the verification of the system. Between the axes of the V-model bypasses are possible.

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 18 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt ImplementationVerification architecture void P1(a, b) { y = a + b * c; … } executable specification models virtual prototypes system complexity design complexity process complexity model complexity V-model for design and verification

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 19 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt For the design of complex embedded systems, a generic architecture of the Hardware/Software system is proposed. A generic architecture reduces the complexity of the design process for embedded systems. The mapping of the system specification to the architecture can be automated and supported by software tools, if a generic architecture exists. These tools are within the hardware synthesis, communication synthesis and software compilation. A generic system architecture

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 20 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt A generic architecture consists of: one or multiple processor cores, a communication- (switching) network some digital hardware, mainly reconfigurable (FPGA). In typical SOC applications this generic architecture is extended by further components as e.g.: analog components, sensors and actuators and/or optical components. A generic system architecture

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 21 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Hardware/Software- System-specification Hardware/Software- partitioning Communication- synthesis Hardware- synthesis Software- compilation FPGA Processor FPGA Processor Switching network Processor core Field Programmable Gate Arrays Design process for a generic chip architecture Generic chip architecture

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 22 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt To simplify the combined hard- and software development approach, one could introduce ideas and experiences from software to hardware development: Define a “High-Level-Hardware-Descriptionlanguage” introducing the following well known concepts from software development: object orientation inheritance reuse Design languages

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 23 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt Examples: SystemC:Open System C Initiative SystemVeriLog:System Verilog Organization Cynthesizer:Forte Design Systems Design languages

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 24 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt SystemC ist very similar to C++ Advantages: Hardware components can be defined as objects with interfaces and functionality Similar languages for soft- and hardware developmant enable synergetic effects Common tools for soft- and hardware development can be used Data exchange is simplified High level verification is enabled by using formal high level languages Design languages

Hier wird Wissen Wirklichkeit Computer Architecture – Part 5 – page 25 of 25 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt SystemC AMS (Analog Mixed Signals) is a SystemC extension. It supports the implementation of heterogeneous hardware/ software systems. Analog Circuits (CT-NET) DSP+Software (SDF) Digital Hardware (discrete event) a + 1 SystemC AMS Will support combination of different models of computation and solvers Intelligent, adaptive interfaces C++ library Modeling and refinement of communication Discrete event simulation kernel Design languages