Principle Behind Hierarchical Storage  Each level memorizes values stored at lower levels  Instead of paying the full latency for the “furthermost” level of storage each time Effective Access T i = h i t i + (1 - h i ) T i+1  where h i is the ‘hit’ ratio, the probability of finding the desired data memoized at level i  t i is the raw access time of memory at level i  Given a program with good locality of reference S working-set < s i  h i  1  T i  t i  A balanced system achieves the best of both worlds ­the performance of higher-level storage ­the capacity of lower-level low-cost storage. Assumption: faster memory is more expensive

Caching vs Demand Paging CPU cache primary memory primary memory secondary memory cachingdemand paging cache entrypage-frame cache block (~16 bytes)page (~4k bytes) cache miss (1% to 20%)page miss (~.001%) cache hit (~1 cycle)page hit (~10 cycles) cache miss (~10 cycles)page miss(~10K cycles) a miss is handled in a miss is handled mostly in hardware software

Modern Virtual Memory Systems: illusion of a large, private, uniform store Demand Paging capacity of secondary memory at the speed of primary memory Address Translation dynamic relocation large “perceived” address space Protection several users, each with their private address space and a common system space VAPA map -ping OS user i Primary Memory Swapping Store

Virtual to Physical Address Translation decoder Physical Address Virtual Address Main Memory PA = f(VA) Swap Disk

Page-Based Virtual Memory decoder Physical Page Number Translation memory (page table) Page offset Main memory pages Virtual address Virtual page number Physical address Where to hold this translation memory and how much translation memory do we need? (64-bit) (40-bit) (12-bit) (52-bit) (~8-bytes) (1~10 GBytes) (10 ~ 100 GBytes)

Hierarchical Page Table Page Table of the page tables pages of the page table pages page in secondary memory page in primary memory page does not exist p1 p2 P.O. Base of the Page Table of the page tables p1 d p2 effective address processor register 12-bit 10-bit Storage of overhead of translation should be proportional to the size of physical memory and not the virtual address space

Inverted Page Tables hash PID Table Offset Base of Table VPN + PA of IPTE Physical Memory VPN PID PTE Inverted Page Table Size of Inverted Page table only needs to be proportional to the size of the physical memory Each VPN can only be mapped to a small set of entries according to a hash function To translate a VPN, check all allowed table entries for matching VPN and PID How many memory lookup per translation?

Translation Look-aside Buffer (TLB) = Index Tag Physical page no. Physical address Page offset Virtual address Virtual page no. Page offset A cache of address translations

tag idx Set-Associative and Fully Associative TLBs   Physical address Page offset Virtual page no. PPN tag Phy. pg. no. page offset tag     Virtual page no. Physical address Page offset PPN tag Phy. pg. no. page offset What are relative sizes of ITLB, BTB and I-cache?