Faculty of Computer Science © 2006 CMPUT 229 Buses and Memories And Adders.

Slides:

Advertisements

Similar presentations

Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika

Advertisements

Modular Combinational Logic

CSE-221 Digital Logic Design (DLD)

Faculty of Computer Science © 2006 CMPUT 229 Memory Hierarchy Part 1 Refreshing Memory.

The Structure of the CPU

TopicF: Static and Dynamic Memories José Nelson Amaral

CMPUT Computer Organization and Architecture I1 CMPUT229 - Fall 2003 Topic D: The Memory Hierarchy José Nelson Amaral.

Faculty of Computer Science © 2006 CMPUT 229 Digital Logic From Switches to Memories.

1 EE365 Three-state Outputs Encoders Multiplexers XOR gates.

Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks.

Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.

1 EE 365 Adders Multipliers Read-Only Memories 2 Equality Comparators 1-bit comparator 4-bit comparator EQ_L.

EE365 Adv. Digital Circuit Design Clarkson University Lecture #8 Buffers, Drivers, Encoders, MUXs & XORs.

Main Memory by J. Nelson Amaral.

Faculty of Computer Science © 2006 CMPUT 229 Special-Purpose Codes Binary, BCD, Hamming, Gray, EDC, ECC.

Adders, subtractors, ALUs

EECS 370 Discussion 1 xkcd.com. EECS 370 Discussion Topics Today: – Floating Point – Finite State Machines – Combinational Logic – Sequential Logic 2.

Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Logic Circuits I.

+ CS 325: CS Hardware and Software Organization and Architecture Combinational Circuits 1.

Digital Components and Combinational Circuits Sachin Kharady.

Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.

WEEK #10 FUNCTIONS OF COMBINATIONAL LOGIC (ADDERS)

Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Logic Circuits I.

Arithmetic Building Blocks

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic9: Three-State Buffers, Encoders/Decoders José Nelson Amaral.

CMPUT 429/CMPE Computer Systems and Architecture1 CMPUT429 - Winter 2002 Topic5: Memory Technology José Nelson Amaral.

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs.

Multiplexers XOR gates. Multiplexers A multiplexer is a digital switch - it connects data from one of n sources to its output. An n-input and b-bit multiplexer.

1 EE121 John Wakerly Lecture #6 Three-state Outputs Encoders Multiplexers XOR gates.

Lecture 9 Topics: –Combinational circuits Basic concepts Examples of typical combinational circuits –Half-adder –Full-adder –Ripple-Carry adder –Decoder.

Memory Devices May be classified as: Connections: ROM; Flash; SRAM;

CSE115: Digital Design Lecture 20: Comparators, Adders and Subtractors Faculty of Engineering.

L26 – Datapath ALU implementation

Logic Gates Logic gates are electronic digital circuit perform logic functions. Commonly expected logic functions are already having the corresponding.

Nov 10, 2008ECE 561 Lecture 151 Adders. Nov 10, 2008ECE 561 Lecture 152 Adders Basic Ripple Adders Faster Adders Sequential Adders.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors,

4. Computer Maths and Logic 4.2 Boolean Logic Logic Circuits.

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

EE365 Adv. Digital Circuit Design Clarkson University Lecture #9 Math Units ROMs.

Universal college of engineering & technology. .By Harsh Patel)

EE121 John Wakerly Lecture #6

1 Ethics of Computing MONT 113G, Spring 2012 Session 5 Binary Addition.

BR 8/991 Combinational Building Blocks 2/1 Multiplexor (MUX) I0 I1 Y S if S = 0, then Y = I0 if S = 1, then Y = I1 Y = I0 S’ + I1 S I0 I1 Y S A[3:0] B[3:0]

Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks.

CEC 220 Digital Circuit Design More VHDL Fri, February 27 CEC 220 Digital Circuit Design Slide 1 of 15.

1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.

CMPUT Computer Organization and Architecture I1 CMPUT229 - Fall 2002 Topic 2: Digital Logic Structure José Nelson Amaral.

How does a Computer Add ? Logic Gates within chips: AND Gate A B Output OR Gate A B Output A B A B

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Adders,subtractors, ALUs.

4–1. BSCS 5 th Semester Introduction Logic diagram: a graphical representation of a circuit –Each type of gate is represented by a specific graphical.

1 The ALU l ALU includes combinational logic. –Combinational logic  a change in inputs directly causes a change in output, after a characteristic delay.

ECEN 248 Lab 3: Study and Implementation of Adders Dept. of Electrical and Computer Engineering.

Combinational Circuits

A question of science Circuit Symbols

Digital Components and Combinational Circuits

Summary Half-Adder Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out.

Combinatorial Logic Design Practices

CSE Winter 2001 – Arithmetic Unit - 1

FIGURE 4.1 Block diagram of combinational circuit

Number Systems and Circuits for Addition

DIGITAL ELECTRONICS B.SC FY

Combinational Circuits

XOR Function Logic Symbol  Description  Truth Table 

Adder Circuits By: Asst Lec. Basma Nazar

Digital Circuits and Logic

Lecture 3 Combinational units. Adders

Computer Architecture

Presentation transcript:

Faculty of Computer Science © 2006 CMPUT 229 Buses and Memories And Adders

© 2006 Department of Computing Science CMPUT 229 Adders  Basic building block is “full adder” –1-bit-wide adder, produces sum and carry outputs Cout is one if two or more of the inputs are one. S is one if an odd number of inputs are one.

© 2006 Department of Computing Science CMPUT 229 Full-adder circuit

© 2006 Department of Computing Science CMPUT 229 Ripple adder –Speed limited by carry chain –Faster adders eliminate or limit carry chain 2-level AND-OR logic ==> 2 n product terms 3 or 4 levels of logic, carry lookahead

© 2006 Department of Computing Science CMPUT 229 A bi-stable circuit  How to control it? –Control inputs  S-R latch

© 2006 Department of Computing Science CMPUT 229 D latch

© 2006 Department of Computing Science CMPUT 229 Functional Units and Buses Clements, pp. 88 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

© 2006 Department of Computing Science CMPUT 229 Connection of Systems to a Bus Clements, pp. 88 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

© 2006 Department of Computing Science CMPUT 229 Outputs Cannot Simply be Connected Together Clements, pp. 89 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

© 2006 Department of Computing Science CMPUT 229 Tri-state Outputs Clements, pp. 89 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

© 2006 Department of Computing Science CMPUT 229 Symbols for tri-state buffers Clements, pp. 90 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

© 2006 Department of Computing Science CMPUT 229 Interconnections with Tri-state Buffers Clements, pp. 101 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3DOUT2DOUT1DOUT0 3-to-8 decoder A2 A1 A DIN3DIN0DIN2DIN1 WE_L CS_L OE_L WR_L IOE_L

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder A2 A1 A DIN3 WE_L CS_L OE_L WR_L IOE_L

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder A2 A1 A DIN3 WE_L CS_L OE_L WR_L IOE_L

IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder A2 A1 A DIN3 WE_L CS_L OE_L WR_L IOE_L