Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 6: January 29, 2007 VLSI Scaling

Penn ESE Spring DeHon 2 Today VLSI Scaling Rules Effects Historical/predicted scaling Variations (cheating) Limits

Penn ESE Spring DeHon 3 Why Care? In this game, we must be able to predict the future Rapid technology advance Reason about changes and trends re-evaluate prior solutions given technology at time X.

Penn ESE Spring DeHon 4 Why Care Cannot compare against what competitor does today –but what they can do at time you can ship Careful not to fall off curve –lose out to someone who can stay on curve

Penn ESE Spring DeHon 5 Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters:   (lambda) -- Mead and Conway (class)  S -- Bohr  1/  -- Dennard

Penn ESE Spring DeHon 6 Feature Size is half the minimum feature size in a VLSI process [minimum feature usually channel width]

Penn ESE Spring DeHon 7 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)

Penn ESE Spring DeHon 8 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltage (V)

Penn ESE Spring DeHon 9 Effects? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (  gd ) Wire Delay (  wire ) Power

Penn ESE Spring DeHon 10 Area       L * W       130nm   90nm  50% area  2× capacity same area

Penn ESE Spring DeHon 11 Area Perspective

Penn ESE Spring DeHon 12 Capacity Scaling from Intel

Penn ESE Spring DeHon 13 ITRS 2005 Moore’s Law

Penn ESE Spring DeHon 14 Capacitance Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   T ox /  –C ox   C ox

Penn ESE Spring DeHon 15 Capacitance Gate Capacitance  C gate = A*C ox       C ox   C ox  C gate   C gate / 

Penn ESE Spring DeHon 16 Threshold Voltage

Penn ESE Spring DeHon 17 Threshold Voltage V TH   V TH 

Penn ESE Spring DeHon 18 Current Saturation Current I d =(  C OX /2)(W/L)(V gs -V TH ) 2 V gs= V   V  V TH   V TH  W   W  L   L  C ox   C ox I d   I d 

Penn ESE Spring DeHon 19 Gate Delay   gd =Q/I=(CV)/I  V   V   I d   I d  C C /C C /   gd   gd / 

20 Overall Scaling Results, Transistor Speed and Leakage. Preliminary Data from 2005 ITRS. Intrinsic Transistor Delay,  CV/I (lower delay = higher speed) Leakage Current (HP: standby power dissipation issues) HP  Target: 17%/yr, historical rate LOP LSTP LSTP  Target: Isd,leak ~ 10 pA/um LOP HP HP = High-Performance Logic LOP = Low Operating Power Logic LSTP = Low Standby Power Logic 17%/yr rate Planar Bulk MOSFETs Advanced MOSFETs

Penn ESE Spring DeHon 21 Resistance R=  L/(W*t) W   W  L, t similar R   R

Penn ESE Spring DeHon 22 Wire Delay   wire =R  C  R  R  C  C /    wire  wire …assuming (logical) wire lengths remain constant... Assume short wire or buffered wire (unbuffered wire ultimately scales as length squared)

Penn ESE Spring DeHon 23 Power Dissipation (Static Load) Resistive Power –P=V*I –V   V  –I d   I d  –P   P  

Penn ESE Spring DeHon 24 Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V   C   C /   P   P   Increase Frequency?   gd   gd /   So: f   f ?  P   P  

Penn ESE Spring DeHon 25 …and leakage [source: Borkar/Intel, Micro37, 12/04]

Penn ESE Spring DeHon 26 Intel on Leakage [source: Borkar/Intel, Micro37, 12/04]

Penn ESE Spring DeHon 27 Effects? Area 1/   Capacitance 1/  Resistance  Threshold (V th ) 1/  Current (I d ) 1/  Gate Delay (  gd ) 1/  Wire Delay (  wire ) 1 Power 1/     1/  

Penn ESE Spring DeHon 28 ITRS Roadmap Semiconductor Industry rides this scaling curve Try to predict where industry going –(requirements…self fulfilling prophecy)

Penn ESE Spring DeHon 29 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Penn ESE Spring DeHon 30 Half Pitch (= Pitch/2) Definition (Typical MPU/ASIC) (Typical DRAM) Poly Pitch Metal Pitch Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Penn ESE Spring DeHon > 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> x 0.7x NN+1N+2 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% * CARR(T) = Compound Annual Reduction Rate cycle time period, T) Log Half-Pitch Linear Time 1994 NTRS -.7x/3yrs Actual -.7x/2yrs Scaling Calculator + Node Cycle Time: Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Penn ESE Spring DeHon 32 ITRS 2005

Penn ESE Spring DeHon 33 ITRS 2003,2005 Gate/Wire Scaling

Penn ESE Spring DeHon 34 What happens to delays? If delays in gates/switching? If delays in interconnect? Logical interconnect lengths?

Penn ESE Spring DeHon 35 Delays? If delays in gates/switching? –Delay reduce with 1/ 

Penn ESE Spring DeHon 36 Delays Logical capacities growing Wirelengths? –No locality: L   (slower!) –Rent’s Rule L   n (p-0.5) [p>0.5]

Penn ESE Spring DeHon 37 Compute Density Density = compute / (Area * Time)   >compute density scaling>     gates dominate, p<0.5    moderate p, good fraction of gate delay –[p from Rent’s Rule again – more on Day14]    large p (wires dominate area and delay)

Penn ESE Spring DeHon 38 Power Density P  P   (static, or increase frequency) P  P   (dynamic, same freq.) A  A   P/A   P/A … or … P/  A

Penn ESE Spring DeHon 39 Cheating… Don’t like some of the implications –High resistance wires –Higher capacitance –Quantum tunneling –Need for more wiring –Not scale speed fast enough

Penn ESE Spring DeHon 40 Improving Resistance R=  L/(W*t) W   W  L, t similar R   R  Don’t scale t quite as fast.  Decrease  (copper)

Penn ESE Spring DeHon 41

Penn ESE Spring DeHon 42 Capacitance and Leakage Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   T ox /  –C ox   C ox Reduce Dielectric Constant  (interconnect) and Increase Dielectric to substitute for scaling T ox (gate quantum tunneling)

Penn ESE Spring DeHon 43 Threshold Voltage

Penn ESE Spring DeHon 44 ITRS 2005

Penn ESE Spring DeHon 45 High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P

Penn ESE Spring DeHon 46 Intel Saturday NYT Announcement Intel Says Chips Will Run Faster, Using Less Power –NYT 1/27/07, John Markov –Claim: “most significant change in the materials used to manufacture silicon chips since Intel pioneered the modern integrated- circuit transistor more than four decades ago” –“Intel’s advance was in part in finding a new insulator composed of an alloy of hafnium…will replace the use of silicon dioxide.”

Penn ESE Spring DeHon 47 Wire Layers = More Wiring

Penn ESE Spring DeHon 48 [ITRS2005 Interconnect Chapter] Typical chip cross-section illustrating hierarchical scaling methodology

Penn ESE Spring DeHon 49 Improving Gate Delay   gd =Q/I=(CV)/I  V   V   I d =(  C OX /2)(W/L)(V gs -V TH ) 2  I d   I d  C C /C C /   gd   gd /   Lower C.  Don’t scale V. Don’t scale V: V  V I   I  gd   gd /  2

Penn ESE Spring DeHon 50 …But Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V   C   C /   P   P   Increase Frequency?  f   f ?  P   P   If not scale V, power dissipation not scale.

Penn ESE Spring DeHon 51 …And Power Density P   P (increase frequency) P   P   (dynamic, same freq.)     P/A   P/A … or …   P/A Power Density Increases …this is where some companies have gotten into trouble…

Penn ESE Spring DeHon 52 Intel on Leakage [source: Borkar/Intel, Micro37, 12/04]

Penn ESE Spring DeHon 53 Physical Limits Doping? Features?

Penn ESE Spring DeHon 54 Physical Limits Depended on –bulk effects doping current (many electrons) mean free path in conductor –localized to conductors Eventually –single electrons, atoms –distances close enough to allow tunneling

Penn ESE Spring DeHon 55 Dopants/Transistor Technology Node (nm) Mean Number of Dopant Atoms

Penn ESE Spring DeHon 56 Electrons e=1.6× C How many electrons?

Penn ESE Spring DeHon 57 What Is A “Red Brick” ? Red Brick = ITRS Technology Requirement with no known solution Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment [from Andrew Kahng]

Penn ESE Spring DeHon 58 The “ Red Brick Wall ” ITRS vs 1999 Source: Semiconductor International - [from Andrew Kahng]

Penn ESE Spring DeHon 59 ITRS 2005 …

Penn ESE Spring DeHon 60 Conventional Scaling Ends in your lifetime …perhaps in your first few years out of school… Perhaps already: –"Basically, this is the end of scaling.” May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group

Penn ESE Spring DeHon 61 Finishing Up...

Penn ESE Spring DeHon 62 Big Ideas [MSB Ideas] Moderately predictable VLSI Scaling –unprecedented capacities/capability growth for engineered systems –change –be prepared to exploit –account for in comparing across time –…but not for much longer

Penn ESE Spring DeHon 63 Big Ideas [MSB-1 Ideas] Uniform scaling reasonably accurate for past couple of decades Area increase   –Real capacity maybe a little less? Gate delay decreases (1/  ) Wire delay not decrease, maybe increase Overall delay decrease less than (1/  )