General Electronics for Time projection chambers GET a Multi-Project for IRFU/SPhN, GANIL, GSI, Compostela, CENBG, NSCL/MSU, Darsebury, York General Electronics for Time projection chambers GET a Multi-Project for IRFU/SPhN, GANIL, GSI, Compostela, CENBG, NSCL/MSU, Darsebury, York Emanuel Pollacco Liverpool ACTAR Dec 2008

1.ACTAR –Active Target –Saclay & GANIL & Darsebury, Compostel, GSI, York … 2.2p - TPC –Particle decay –CENBG 3.AT-TPC –Fragmentation (  +,  - ) & Active-Target - Magnet –MSU 4.R3B-TPC –Heavy projectile fragmentation – Magnet* –Saclay & R3B collaboration 5.SAMURAI-TPC –Fragmentation (  +,  - ) - Magnet –Riken, Kyoto University, … Individually, the labs will not be able to build the instruments to perform the experiments- Costs/engineers Multi-Project & Multi-Laboratory Emanuel Pollacco Liverpool ACTAR Dec 2008

FP6 – ACTAR program Physics – Yellow Book Detector Simulations Gases & Gas Amplification tests Electronic system studies Principle element of the project To design and build a prototype for general nuclear physics TPCs electronics. System will be an assessment standard for medium size and high throughput system for Nucl. Phys. Multi-Project & Multi-Laboratory Nuclear Particle Spectroscopy Direct Reactions Resonant Reactions Decay Spallation Fragmentation Physics Programs Emanuel Pollacco Liverpool ACTAR Dec 2008

FP6 – ACTAR program Physics – Yellow Book Detector Simulations Gases & Gas Amplification tests Electronic system studies Principle element of the project To design and build a prototype for general nuclear physics TPCs electronics. System will be an assessment standard for medium size and high throughput system for Nucl. Phys. Multi-Project & Multi-Laboratory Emanuel Pollacco Liverpool ACTAR Dec 2008

FP6 – ACTAR program Physics – Yellow Book Detector Simulations Gases & Gas Amplification tests Electronic system studies Principle element of the project To draw a detailed Conceptual Design, Build & Test a prototype for general nuclear physics TPCs electronics. System will be an assessment standard for medium size and high throughput system for Nucl. Phys. Multi-Project & Multi-Laboratory Medium Sized System Multiple Applications Modular/Scale-Free Very High Dynamic Range High through-put for low occupation events Nucl. Phys. Based Emanuel Pollacco Liverpool ACTAR Dec 2008

Emanuel Pollacco FP6 – ACTAR program Physics – Yellow Book Detector Simulations Gases & Gas Amplification tests Electronic system studies Principle element of the project To draw a detailed Conceptual Design, Build & Test a prototype for general nuclear physics TPCs electronics. System will be an assessment standard for medium size and high throughput system for Nucl. Phys. Multi-Project & Multi-Laboratory

High S/N ratio Low Threshold (  ) High Dynamic Range (U) Resol n Charge; Time; Position Internal Trigger Selective Readout Zero Suppress Base-Line Correction Time Stamp Automated Calibration Beam e Measure Q(t), X, Y per Pad Sampling ADC anode wire gating grid  ZAP  PA GET Emanuel Pollacco Liverpool ACTAR Dec 2008

4.Gbit/s Max in 4x2.Gbit/s Max in 288 Pads/PA 1.Gbit/s Max out FPGA Trigger Selective/ Calculated -Read out FPGA PCI Express Event-Building CoBo InBo Time-Stamp Zero Suppress Base-Line Corr Ordering  LVDS PA ZAP-  PA A Simple Architecture To Give Scale ‘Free’ Modular Portable - different labs Automated PA ZAP-  ZAP  ZAP-  1.Gbit/s Max 25Mhz -FADC – 12bits AsAd PA-72 ASIC Emanuel Pollacco Liverpool ACTAR Dec 2008

ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASIC AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASIC AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASIC AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASIC AsAd x10 5 Pads Samples FPGA MUTANT LVDS Optic PCI FPGA InBo FPGA CoBo BEN  GANIL MSU GANIL/MSU CENBG/CEA Emanuel Pollacco Liverpool ACTAR Dec 2008

PCI FPGA ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd 3456 Pads FPGA Trigger FPGA ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd FPGA ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd ZAP-72 PA-72 ZAP-72 PA-72 ZAP-72PA-72 ZAP-72 PA-72 25Mhz -FADC - 4 ASICASIC  AsAd PCI Exp BEN  Emanuel Pollacco Liverpool ACTAR Dec 2008

FPGA 14,000 Pads – 7x10 6 Samples – 150 watts Trigger FPGA BEN Other Sub-systems  IOLAN Ethernet PCI Exp Event Rates 1KHz FPGA Emanuel Pollacco Liverpool ACTAR Dec 2008

ASIC for GET Based on the T2K Program

15 GeV/c p-Pb (# 20K events) FE electronics validated on 1728 channels ) HARP test set-up at CERN (oct 07 ) SEDI/IRFU

Filter 511 cells Disc Pulser ADC Slow Control Power Clock X 76 SPY Generic Aspects via Slow Control Memory Bank Select External PA + Filter Adjustable Sample Size & Frequency ADC parameters Internal Trigger Calculated Read-Out Pattern Pattern/Trigger PA PA + Filter 1) 72 +/- input 2) 16 shaping times 3) Adjustable gain/ch

c0c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 c0c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 Channel 0 c0 c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 c0c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 c0c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 c0 c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 Channel 1 Channel n Channel 72 Circular memory Channels 72 Cells 511 Write freq: 1 to 100 MHz Precision: 12 bits Store: 2msec Read: 25 MHz FADC Precision: 12 bits Read: 128/256/ 511 5/ 10/ 20 µsec Read: 360/720/1440 µsec < All Total read Time: Read 36/ 72/ 144 µsec < 10% trigger Total read Time: 100 to 500µsec

An Overview 2 Clock Syn. External Trigger CoBo BEM VX4 AsAd VX5ADC AGET InBo PCI exp Memory X36 X9 X4 Fast Ethernet Slow Control NIM Crate(s) X4 Pulser V & I Temp PA X10 4 PC MUTANT VX4 

Trigger A Trigger which gives the Multiplicity –Discriminators LE – adj dead time –Integrated at 20MHz pipe lined to Vertex 5 –Adjustable sliding time window – ~ Drift Time =  T Channel fired ~ Drift Time =  T DRIFT TIME N Trigger

ToT 1: % Improvement 1-200MHz 12 & 14 bits <5kHz

Gains & Losses with an Active Target X5 to X40 in luminosity Very low EPI thresholds to 0.1 MeV E<E T ~ Efficiency 90% for low energy E T ejectile. Energy resol n < 50keV For Z=1 & 2, mass & charge resol n for <E T. Angular resol n = Nouvelle method  Nouvelle discoveries! Instrument adoptable to a number of techniques Limited max. energy 4 MeV.A within the TPC.  Coupling to MUST2 No Gamma coincidence E>E T ~ Efficiency 40% Complex Front End Electronics High data capture To develop data analysis techniques for Nucl. Phys Coupling MUST2 &Physics prog.