Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007.

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Presentation transcript:

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007

Last time: Lecture 02: CMOS Logic What is a VLSI system? What is a VLSI system composed of? How many? The life cycle of IC design Topics covered in the class Today: Simple descriptions of nMOS and pMOS transistors How to build logic gates from these devices?

Impact of doping on silicon resistivity dope with phosphorous or arsenic  n-type dope with boron  p-type silicon  atoms in cm 3 Resistivity 3.2  10 5 Ωcm 1 atom in billion  88.6 Ωcm 1 atom in million  Ωcm 1 atom in thousand  Ωcm 1 atom in billion  Ωcm 1 atom in million  Ωcm 1 atom in thousand  Ωcm  Electrons are more mobile/faster than holes

What happens if we sandwich p & n types? n p A B Al One-dimensional representation

More sandwiches: nMOS transistor g=0: When the gate is at a low voltage (V GS < V T ):  p-type body is at low voltage  source and drain-junctions diodes are OFF  transistor is OFF, no current flows g=1: When the gate is at a high voltage (V GS ≥ V T ):  negative charge attracted to body  inverts a channel under gate to n-type  transistor ON, current flows

nMOS pass ‘0’ more strongly than ‘1’ Why does ‘1’ pass degraded?

More sandwiches: pMOS transistor g=0: When the gate is at a low voltage (V SG < V T ):  positive charge attracted to body  inverts a channel under gate to p-type  transistor ON, current flows g=1: When the gate is at a high voltage (V SG ≥ V T ):  negative charge attracted to body  source and drain junctions are OFF  transistor OFF, no current flows

pMOS pass ‘1’ more strongly than ‘0’ Why does ‘0’ pass degraded?

An nMOS and pMOS make up an inverter pMOS + nMOS = CMOS

More CMOS gates What is this gate function? What’s wrong about this design?

3-input NANDs

Series-Parallel Combinations

What are the transistor schematics of the NOR gate?

AOI

Transmission gate

MUX

Latch design

Flip-flop (edge triggered) design

Summary We studied CMOS gate structure but we do not know they get fabricated or how fast they are Next time: CMOS fabrication