Uli Schäfer JEM Status and plans Firmware -Algorithms -Tools -Status Hardware -JEM1 -Status Plans

Uli Schäfer Algorithms (RTDP) Minor modifications to energy sum algorithm due to re- partitioning on JEM1: Receive energies 4×8 ×(e/h) plus overlap (total 88 ch.) Synchronisation, parity, mask Generate jet elements E T =E e +E h, low threshold Saturate jet elements at 1 TeV and send to jet 5-bit wide From jet elements (E T ) calculate E X and E Y by multiplying cosφ, sinφ (accuracy: 10bit E T ×12-bit coefficient -> 10 bit) Threshold E T Pre-sum E X, E Y and E T : 12 jet elements (JEM0:4) Saturate at 4 TeV Send to sum 40Mb/s (JEM0:80Mb/s) Final summation over 3 partial sums (JEM0:8) Quad-linear encoding of energies (8 bit, 4 TeV range) Saturation (4TeV) Parity

Uli Schäfer Firmware modifications For JEM1 some modifications are required, mainly in I/O stages (DDR registers), block RAM, DLLs, hardware multipliers, clock mirror, FCAL handling, E X /E Y calculation on input processor, separate sum processor, VME access. Change of channel count per input processor Work started : complete re-write of input processor, since previous version was hard-coded for 8 channels; instantiations, no loops.  Coherent code for both JEM0 and JEM1  debug on JEM0 and hope for plug and play once JEM1 arrives (JEM1 code can run on input processors only while jet algorithm is switched off) VME register map completely refurbished  adapt on-line software ! The firmware was re-written using pure VHDL, few instantiations, mainly behavioural sequential code.  independent of the choice of synthesis tool  guaranteed to be maintainable throughout ATLAS lifetime.

Uli Schäfer Tools Mentor Graphics stopped making regular updates freely available on the Web. Software updates available via RAL Europractice only ~once per year. Unacceptable situation.  migrate to Xilinx XST synthesis tool. Advantages: Regularly updated via ISE service packs Supports automatic register balancing Seems to be better at inferring I/O flip-flops from behavioural sequential code Disadvantages: Does not automatically infer balanced adders from behavioural description (cascade rather than tree) s := (others=>’0’); for i in 0 to k-1 loop s:=s+data(i); end loop;  use XST synthesis and describe an adder such that the synthesis tool is persuaded to generate a tree k=4 for i in 0 to k loop --init s(i):=data(i) ; end loop; for i in 0 to k-2 loop --sum s(k+i):=s(2*i)+s(2*i+1) ; end loop; sum:=s(2*k-2);

Uli Schäfer JEM1 16 x 6-channel de- serialisers : SCAN on 4 Input daughter modules w. XC2V1500. Jet and Sum Processors XC2V2000 (BF package). Configuration : SystemACE

Uli Schäfer JEM1 main board Components : Backplane and daughter connectors (TTC, input) Bus drivers (VME) and ECL line drivers/receivers Jet and Sum processors (BGA 1.28mm pitch) G-links. Opto transmitters One large CPLD SystemACE configurator Voltage converters Front panel connectors/LEDs Production: One-stop Rohde & Schwarz Component procurement PCB production –Adjustment of impedances –Test protocols Assembly –Visual inspection –X-ray

Uli Schäfer H/W Status & Plans H/W Status: Input daughters: 8 PCBs made, 1 assembled, tests due soon. Main board schematic capture 70%, layout 60% finished. JEM0.1 still awaiting re-work (VME backplane pin) Plans: Continue Mainz tests of energy and integrated (J/E) algorithms Next RAL tests Nov./Dec ? –ROD –Sum / jet mergers –Full jet tests (2 JEMs) ? Submit order for JEM1 component procurement along with assembly of remaining input daughters this month Submit JEM1 main board end Dec., back from assembly Feb. Set up stand-alone test bench for input processors after JEM1 submission (  Andrey) to have well-tested daughter modules when JEM1 arrives Keep JEM0s up and running through first stage of slice test Slice test initial requirements : 2 JEM1s and 2 JEM0s (?). Financial situation / module cost  additional JEM1s ?

Uli Schäfer Production plans and risks A minimum of one lab-tested JEM1 to be available by end February. Further JEM1s as required. Risks: Underestimated remaining fraction of schematic capture & layout (possible)  few weeks (disaster money-wise) Component availability (possible)  few weeks Problems with the as yet untested deserialisers (unlikely)  redesign daughters  2.x months Critical analogue components (G-link/opto), TTCdec (?) not JEM specific Main board design errors (possible)  re-submit  1.x months PCB production / assembly problems (unlikely)  ??? Please note that only severe design errors /production problems would prevent JEM1 from being used in initial slice tests. Connectivity problems  use spare tracks (no spare lines to backplane) SystemACE problems  configure via VME CAN problems  run without DCS Risks to volume production : no experience so far  not possible to assess

Uli Schäfer JEP – open questions H/W – urgent – final decision on opto transmitter F/W – medium term: Slice data G-link format: do we change over to 6 input channels per G-link bit to allow for readout of 6 ticks worth of data at full rate? No simple mapping of input channels to input processors in (η,φ) due to limitations on routing of high-speed tracks (length, vias). Do we sort it out in –Software (VME channel-address corresponds to location in the input processor), –Firmware (VME address corresponds to (η,φ)), –Re-format slice data in ROC ? Sum CMM : stay with LUT scheme or change to E X *E X +E Y *E Y >=threshold*threshold (might cost ~1/2 tick latency)