1 Chapter 9 Design Constraints and Optimization

2 Overview Constraints are used to influence Synthesizer tool Place-and-route tool The four primary types of constraints Synthesis I/O Timing Area/Location

3 Overview Synthesis How the synthesis of HDL code to RTL occurs I/O constraints Assign a signal to a specific I/O (pin) or I/O bank Timing constraints Area/Location

4 Design Constraint Management Constraint implementation issue The wide range of potential configuration overlap and interference Effective design constraint implementation requires A solid knowledge and understanding of both the system requirements and the current design implementation approach

5 Synthesis Constraints Synthesis constraints are used to direct the synthesis tool to perform specific operation Two important synthesis constraints REGISTER_BALANCING INCREMENTAL_SYNTHESIS Reduce the total time it take to compile the design

6 XST Synthesis Constraints

7 Pin Constraints Effective pin assignment requires detailed system-level design knowledge, including Board-level component relationships and interface details Targeted FPGA architecture details and proposed FPGA-level design implementation

8 FPGA Clock Design Guidelines Separate FPGA clocks into priority groups Assign the highest priority clocks first Assign clock block management resources Manage lower priority clocks

9 Timing Constraints Identify and constrain system clocks Identify and create signal path groups Assign global constraints Assign detailed group and individual path constraints

10 Input Timing Constraint

11 Output Timing Constraint

12 Area Constraints and Floorplanning Area constraints may also define a potential placement region for design elements

13 Design Optimization

14 Q & A