ECE 232 L15.Miulticycle.1 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers ECE 232 Hardware Organization and Design Lecture 15 Multi-cycle Processor, contd Maciej Ciesielski

ECE 232 L15.Miulticycle.2 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Outline °Review of midterm exam I Problematic questions: Overflow detection, MIPS assembly, delay computation °FSM-based control, cont’d Where are we in processor design: physical TR’s Deriving control logic

ECE 232 L15.Miulticycle.3 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Recall: Step-by-step Processor Design Step 1: ISA => Logical Register Transfers Step 2: Components of the Datapath Step 3: RTL + Components => Datapath Step 4: Datapath + Logical RTs => Physical RTs Step 5: Physical RTs => Control

ECE 232 L15.Miulticycle.4 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Step 4: R-type (add, sub,...) °Logical Register Transfer °Physical Register Transfers inst Logical Register Transfers ADDUR[rd] <– R[rs] + R[rt]; PC <– PC + 4 inst Physical Register Transfers IR <– MEM[pc] ADDUA<– R[rs]; B <– R[rt] S <– A + B R[rd] <– S; PC <– PC + 4 Exec Reg. File Mem Access Data Mem A B S M Reg File Equal PC Next PC IR Inst. Mem

ECE 232 L15.Miulticycle.5 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Step 4: Logical immediate °Logical Register Transfer °Physical Register Transfers inst Logical Register Transfers ORIR[rt] <– R[rs] OR zx(Im16); PC <– PC + 4 inst Physical Register Transfers IR <– MEM[pc] ORIA<– R[rs]; B <– R[rt] S <– A or ZeroExt(Im16) R[rt] <– S; PC <– PC + 4 Exec Reg. File Mem Access Data Mem A B S M Reg File Equal PC Next PC IR Inst. Mem

ECE 232 L15.Miulticycle.6 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Step 4 : Load °Logical Register Transfer °Physical Register Transfers inst Logical Register Transfers LWR[rt] <– MEM(R[rs] + sx(Im16); PC <– PC + 4 inst Physical Register Transfers IR <– MEM[pc] LWA<– R[rs]; B <– R[rt] S <– A + SignEx(Im16) M <– MEM[S] R[rd] <– M; PC <– PC + 4 Exec Reg. File Mem Access Data Mem A B S M Reg File Equal PC Next PC IR Inst. Mem

ECE 232 L15.Miulticycle.7 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Step 4 : Store °Logical Register Transfer °Physical Register Transfers inst Logical Register Transfers SWMEM(R[rs] + sx(Im16) <– R[rt];PC <– PC + 4 inst Physical Register Transfers IR <– MEM[pc] SWA<– R[rs]; B <– R[rt] S <– A + SignEx(Im16); MEM[S] <– BPC <– PC + 4 Exec Reg. File Mem Access Data Mem A B S M Reg File Equal PC Next PC IR Inst. Mem

ECE 232 L15.Miulticycle.8 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Step 4 : Branch °Logical Register Transfer °Physical Register Transfers inst Logical Register Transfers BEQif R[rs] == R[rt] then PC <= PC + sx(Im16) || 00 else PC <= PC + 4 inst Physical Register Transfers IR <– MEM[pc] BEQ|EqPC <– PC + 4 inst Physical Register Transfers IR <– MEM[pc] BEQ|EqPC <– PC + sx(Im16) || 00 Exec Reg. File Mem Access Data Mem ABSM Reg File Equal PC Next PC IR Inst. Mem

ECE 232 L15.Miulticycle.9 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Alternative datapath (book): Multiple Cycle Datapath °Miminizes hardware: 1 memory, 1 adder

ECE 232 L15.Miulticycle.10 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Our Control Model °State specifies control points for Register Transfer °Transfer occurs upon exiting state (same falling edge) Control State Next State Logic Output Logic inputs (conditions) outputs (control points) State X Register Transfer Control Points Depends on Input

ECE 232 L15.Miulticycle.11 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Step 4 => Control Specification for multicycle proc IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ & Equal BEQ & ~Equal PC <= PC + 4 PC <= PC + SX || 00 SW “instruction fetch” “decode / operand fetch” Execute Memory Write-back

ECE 232 L15.Miulticycle.12 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Truth Table stateopcond next state control points next State control points State op Equal datapath State °Translate RTs into control points °Assign states °Build the controller Step 5: Datapath + State Diagram => Control Traditional controller

ECE 232 L15.Miulticycle.13 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Mapping RTs to Control Points IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ & Equal BEQ & ~Equal PC <= PC +4 PC <= PC + SX || 00 SW “instruction fetch” “decode” Execute Memory Write-back imem_rd, IRen ALUfun, Sen RegDst, RegWr, PCen Aen, Ben

ECE 232 L15.Miulticycle.14 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Assigning States IR <= MEM[PC] R-type A <= R[rs] B <= R[rt] S <= A fun B R[rd] <= S PC <= PC + 4 S <= A or ZX R[rt] <= S PC <= PC + 4 ORi S <= A + SX R[rt] <= M PC <= PC + 4 M <= MEM[S] LW S <= A + SX MEM[S] <= B PC <= PC + 4 BEQ & Equal BEQ & ~Equal PC <= PC + 4 PC <= PC + SX || 00 SW “instruction fetch” “decode” Execute Memory Write-back

ECE 232 L15.Miulticycle.15 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Our final Controller FSM Spec “instruction fetch” “decode” Write-back IR <= MEM[PC] PC <= PC A <= R[rs] B <= R[rt] 0001 R-type S <= A fun B R[rd] <= S S <= A op ZX R[rt] <= S ORi S <= A + SX R[rt] <= M M <= MEM[S] LW S <= A + SX MEM[S] <= B SW Execute Memory ~EqualEqual BEQ PC <= PC + SX || S <= A - B move PC incr here

ECE 232 L15.Miulticycle.16 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Detailed Control Specification 0000??????? BEQ BEQ R-typex orIx LWx SWx xxxxxxx xxxxxxx xxxxxxx fun xxxxxxx xxxxxxx or xxxxxxx xxxxxxx add xxxxxxx xxxxxxx xxxxxxx add xxxxxxx StateOp fieldEqNext IRPCOpsExecMemWrite-Back en selA B Ex Sr ALU S R W MM-R Wr Dst R: ORi: LW: SW: -all same in Moore machine

ECE 232 L15.Miulticycle.17 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Performance Evaluation °What is the average CPI? state diagram gives CPI for each instruction type workload gives frequency of each type Type CPI i for type Frequency CPI i x freqI i Arith/Logic440%1.6 Load530%1.5 Store410%0.4 branch320%0.6 Average CPI:4.1

ECE 232 L15.Miulticycle.18 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Summary °Disadvantages of the Single Cycle Processor Long cycle time Cycle time is too long for all instructions except the Load °Multiple Cycle Processor: Divide the instructions into smaller steps Execute each step (instead of the entire instruction) in one cycle °Partition datapath into equal size chunks to minimize cycle time ~10 levels of logic between latches °Follow same 5-step method for designing “real” processor

ECE 232 L15.Miulticycle.19 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers Summary (cont’d) °Control is specified by Finite State Diagram (FSM) °Specialized state-diagrams easily captured by microsequencer simple increment & “branch” fields datapath control fields °Control design reduces to Microprogramming °Control is more complicated with: complex instruction sets restricted datapaths (see the book) °Simple Instruction Set and powerful datapath => simple control could try to reduce hardware (see the book) rather go for speed => many instructions at once!