3/16/2006EECS150 Lab Lecture #91 Chipcon 802.15.4 Transceiver: Q&A Session EECS150 Spring 2006 Lab Lecture #9 David Lin.

Slides:

Advertisements

Similar presentations

Sumitha Ajith Saicharan Bandarupalli Mahesh Borgaonkar.

Advertisements

EECS150 Lab Lecture #61 AC97 PCM Audio EECS150 Fall 2007– Lab Lecture #6 Udam Saini 10/05/2007.

Internal Logic Analyzer Final presentation-part B

Fiber Channel Video Controller uArchitecture Review Tsachy Kapchitz & Michael Grinkrug Super.: Alex Gurevich Technion Digital Lab, Elbit Systems.

2/24/2006EECS150 Lab Lecture #61 N64 Controller (Project Checkpoint#1) EECS150 Spring2006 – Lab Lecture #6 Philip Godoy Guang Yang Greg Gibeling.

Fiber Channel Video Controller Mid-Project Review Tsachy Kapchitz & Michael Grinkrug Super.: Alex Gurovich Technion Digital Lab, Elbit Systems.

3/24/2006EECS150 Lab Lecture #101 Game Engine EECS150 Spring2006 Lab Lecture #10 Guang Yang.

Wireless and going mobile Browsing via low energy photons.

3/10/2006EECS150 Lab Lecture #81 Chipcon Transceiver EECS150 Spring 2006 Lab Lecture #8 David Lin.

CS 300 – Lecture 20 Intro to Computer Architecture / Assembly Language Caches.

1 Lab Session-IV CSIT-120 Spring 2001 Lab 3 Revision and Exercises Rev: Precedence Rules Lab Exercise 4-A Machine Language Programming The “Micro” Machine.

Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.

2/9/2007EECS150 Lab Lecture #41 Debugging EECS150 Spring2007 – Lab Lecture #4 Laura Pelton Greg Gibeling.

1 Lab Session-III CSIT-120 Spring 2001 Revising Previous session Data input and output While loop Exercise Limits and Bounds GOTO SLIDE 13 Lab session.

7/16/2015EECS150 Spring Wireless Transceiver EECS150 Spring 2008 Shah Bawany.

Embedded Programming and Robotics Introduction and Overview Presented by John Cole Senior Lecturer in Computer Science The University of Texas at Dallas,

Final presentation – part B Olga Liberman and Yoav Shvartz Advisor: Moshe Porian April 2013 S YMBOL G ENERATOR 2 semester project.

Computer Organization CS345 David Monismith Based upon notes by Dr. Bill Siever and notes from the Patterson and Hennessy Text.

Chapter 8 – Main Memory (Pgs ). Overview  Everything to do with memory is complicated by the fact that more than 1 program can be in memory.

ECE 493T9 Real Time Embedded System Tutorial Set 2 May 26, Spring 2008.

Lecture 11 Page 1 CS 111 Online Memory Management: Paging and Virtual Memory CS 111 On-Line MS Program Operating Systems Peter Reiher.

Status report 2010/10/22 Atsushi Nukariya. Progress ・ Progress is as follows. 1. Confirm to transfer data from SiTCP to PC. 2. Create software which read.

PROJECT - ZYNQ Yakir Peretz Idan Homri Semester - winter 2014 Duration - one semester.

MIPS I/O and Interrupt.

© 2010 Altera Corporation - Public Lutiac – Small Soft Processors for Small Programs David Galloway and David Lewis November 18, 2010.

LAB 3 – Synchronous Serial Port Design Using Verilog

CSCI 156: Lab 11 Paging. Our Simple Architecture Logical memory space for a process consists of 16 pages of 4k bytes each. Your program thinks it has.

COMP091 – Operating Systems 1 Memory Management. Memory Management Terms Physical address –Actual address as seen by memory unit Logical address –Address.

“Lab. 5” – Updating Lab. 3 to use DMA Test we understand DMA by using some simple memory to memory DMA Make life more interesting, since hardware is involved,

Lecture 4 Page 1 CS 111 Online Modularity and Memory Clearly, programs must have access to memory We need abstractions that give them the required access.

WINLAB Open Cognitive Radio Platform Architecture v1.0 WINLAB – Rutgers University Date : July 27th 2009 Authors : Prasanthi Maddala,

Calliope-Louisa Sotiropoulou FTK: E RROR D ETECTION AND M ONITORING Aristotle University of Thessaloniki FTK WORKSHOP, ALEXANDROUPOLI: 10/03/2014.

Introduction to FPGAs Getting Started with Xilinx.

Functions of Processor Operation Addressing modes Registers i/o module interface Memory module interface Interrupts.

Hardware Description Languages: Verilog

CSC 211 Java I for loops and arrays.

David Kauchak CS 52 – Spring 2017

ECE 353 Lab 3 Pipeline Simulator

MIPS I/O and Interrupt.

Outline Paging Swapping and demand paging Virtual memory.

Digital System Verification

Hardware Description Languages: Verilog

Modularity and Memory Clearly, programs must have access to memory

L7 – Assembler Directives

Video Conferencing System

Getting Started with Programmable Logic

MIPS I/O and Interrupt.

EECS150 Spring 2007 Lab Lecture #9 Neil Warren

Clock Domain Crossing Keon Amini.

MODEM REGISTER VERIFICATION

MIPS I/O and Interrupt.

EECS150 Fall 2007 Lab Lecture #8 Shah Bawany

MODEM REGISTER VERIFICATION

MODEM REGISTER VERIFICATION

CPRE 583 Reconfigurable Computing

MODEM REGISTER VERIFICATION

Logic Analyzers EECS150 Fall Lab Lecture #5 Arjun Singh

Moving Arrays -- 2 Completion of ideas needed for a general and complete program Final concepts needed for Final DMA.

EECS150 Fall 2007 – Lab Lecture #4 Shah Bawany

Debugging EECS150 Fall Lab Lecture #4 Sarah Swisher

COMS 361 Computer Organization

MIPS I/O and Interrupt.

Debugging EECS150 Fall Lab Lecture #4 Sarah Swisher

Bare Metal System Software Development

Good Design & Network Audio

Log in the System 登入系統 Course Selection System: Choose English version.

Logic Analyzers EECS150 Fall Lab Lecture #5 Arjun Singh

Verilog Synthesis & FSMs

AVR Micro controller & Mojo FPGA.

Presentation transcript:

3/16/2006EECS150 Lab Lecture #91 Chipcon Transceiver: Q&A Session EECS150 Spring 2006 Lab Lecture #9 David Lin

3/16/2006EECS150 Lab Lecture #92 Ask Me Questions I’ll be covering some frequent questions. If you have other questions, ask me at any time during the lab lecture.

3/16/2006EECS150 Lab Lecture #93 SPIFifo (1) The code is provided. Take a look, it’s actually pretty simple. Declares FPGA memory: reg [7:0] dataRam[31:0], srcAddrRam[7:0], destAddrRam[7:0]; 8 bits wide each, dataRam has 32 slots, srcAddrRam & destAddrRam have 8 slots Ours it small  uses LUTs. If you increase the size to >= 4096 bits, which is size of 1 BlockRAM, synthesis will use BlockRAM instead.

3/16/2006EECS150 Lab Lecture #94 SPIFifo (2) Two counters act as read & write pointers. WEn enables write counter and saving into all 3 pieces of memory. REn enables read counter. Input is 8-bits  matches size of data coming out of SPI. Output is 32-bits  same as payload size of an entire packet.

3/16/2006EECS150 Lab Lecture #95 SPIFifo (3) As you read data from RX FIFO, save to SPIFifo. Include packet src. & dest. addresses. Saving increments a temporary internal pointer. In input is only for payload! There are separate SrcAddrIn and DestAddrIn inputs. At which point in receiving data from CC2420 is WEn pulsed? After checking CRC, pulse EndSession to make temp. pointer become permanent or DiscardSession to discard the temp. pointer. Full is based on temp. pointer.

3/16/2006EECS150 Lab Lecture #96 Receiving Refers to 2 things: 1. CC2420 is constantly receiving and saving data into RX FIFO as long as it’s not transmitting. Look at CC2420 internal FSM on p You have to “receive” data from RX FIFO, filter it, then save wanted data into SPIFifo.

3/16/2006EECS150 Lab Lecture #97 Post-Transmit Wait Time CC2420 needs 12 symbol periods to move into RX_SFD_SEARCH state after transmit done or SRXON. 1 symbol period = 16 us. Without enforcing wait, aggressive user of your Transceiver module will cause CC2420 to never receive data from air. Not that big of a problem for us  demo game engine transmits once every ~25ms. You want to enforce wait, just in case you forget or make a mistake when doing CP4.

3/16/2006EECS150 Lab Lecture #98 Channel Mapping (k-11), k = 11, …, 26 Your channels range from 0  maps to k = 11.

3/16/2006EECS150 Lab Lecture #99 SPI Remember that SPI has no intelligence. NewData pulses at the same time as InRequest as long as a session has started. Data may or may not be valid. You don’t really need NewData. Inspection of InRequest can give you the same information. You can use NewData as a register enable to retain received data.

3/16/2006EECS150 Lab Lecture #910 What if I’m flying to Mexico to enjoy my spring break? (You know who you are…) Kramnik, kramnik, kramnik! Isn’t Wi-Fi great? Tutorial at: amnik/tutorial.php amnik/tutorial.php You have full access to tools and your U:\. But seriously, get it working before break… We’re not evil (most of the time). It’s for your own good. That said, have a nice break! =)