On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.

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Presentation transcript:

On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng Hailong Yao VLSI CAD LABORATORY UCSD Nov. 24, 2008

2 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Outline  Motivation  Review of Via Count Estimation  Key Parameters to Via Count  Taxonomy of Via Count Modeling Approaches  Verification of Model  Conclusion

3 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Motivation  Via analysis and estimation are of great importance  Yield: via open, high-resistance fault = key defect types  Evaluating performance of existing routers  32nm via rules  Evaluating new technologies or designs  3D implementation needs (via density, …)  Previous work based on “Rent’s parameter”  In this work, we give taxonomy of via modeling and propose a new via count model for placed designs average pins per gate number of terminals number of components Rent’s parameter Landman et al., 1971

4 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Review of Via Count Estimation  Uezono’s model ( T. Uezono et al., ISQED, )  Heavily depends on wire length and track utilization l : estimated wirelength u t : track utilization  Up to 19% error in the experimental results  Questionable argument  Why does #via increase with decreasing Rent’s parameter?  Uezono’s model uses  Davis et al.’s wirelength distribution that has error in #net for length = 1 Correlation between the Rent’s parameter p and the number of vias (Uezono et al., ISQED06) Truncated binomial series in Davis’s model

5 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Key Parameters Affecting Via Count  Experimental setup  For N, k, p, U, M and Tech: use Rentian circuit generator (gnl [1])  For F: use two different clock frequency for AES from opencores.org  For k (in real design): AES SP&R with different cell sets (whole vs. restricted) DOE ParametersValues Number of gates (N) Average terminals per gate (k) Rent’s parameter (p) Placement Utilization (U) Number of metal layers (M) Technology (Tech) 10,000 / 20,000 2 / 3 / 4 / 5 / / 0.3 / 0.5 / 0.7 / % / 70% / 90% 4 / 5 / 6 / 7 /8 90nm / 65nm [1] D. Stroobandt, P. Verplaetse and J. V. Campenhout, "Generating Synthetic Benchmark Circuits for Evaluating CAD Tools", IEEE Trans. On Computer-Aided Design Of Integrated Circuits and Systems, (19)(9) (2000), pp

6 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Sensitivity to Design Parameters  ( Rentian Circuits )  Observations  N   #vias   k   #vias   p   #vias   U   #vias   M   #vias  #vias vs. #instance (N), technology(Tech), #metal (M), and utilization (U) #vias vs. #pins per gate (k), and Rent’s parameter (p) Experimental results show #via increases even for small Rent’s parameters #points to be connected wirelength track utilization

7 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Sensitivity to Design Parameters ( Real Designs )  AES (~15K) core from opencores.org  Clock frequency (F): 50MHz and 400MHz (8X)  #pins per gate (k)  Large-k: use a full set of cells in the library  Small-k: use only INV, BUF, NAND2 and DFF  Wiring pitch (w p ): original, half (2x tracks) DesignFreq.#inst.k#vias Small-k400 MHz Small-k50 MHz Large-k400 MHz Large-k50 MHz PitchWL (um)#vias Original5.19E Half4.66E #via vs. wiring pitch (w p ) #via vs. pins per gate (k) and frequency (F)  #vias increases by 4~11% k increases from 2.7 to 3.6  #vias increases by 44%  #vias decreases by 17%

8 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Summary of Sensitivities to Design Parameters ParametersSensitivity Number of gates(N) Pins per gate (k) Rent’s parameter (p) Placement util. (U) Number of metals (M) Wiring pitch (w p ) Clock frequency (F) Technology (Tech) Strong positive Positive Weak Negative Weak positive Weak negative Routing Congestion or Track Utilization

9 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Via Count Estimation  Key ideas  #vias strongly depends on kN = total #pins  M1 layer generally not used for cell connections  all pins need V12  If no design rules, all routes can be implemented with 1-tier (H/V) of routing layers  No detours and no additional vias  baseline of #vias  Congestion increases #vias

10 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Taxonomy of Via Modeling Approach (1) ① Analytical method  Inputs: given N, k and p  Enable to estimate #vias prior to netlist ② Netlist-based method  Inputs: extracted N, k and p  Parameters are extracted from netlist  better accuracy  Model:  V L : baseline of #vias  V congestion : additional vias from routing congestion  V L calculation  H-BBOX model  #VIA12 = #pins ( )  #VIA23 = #pins  V-BBOX  #VIA12 = #pins  #VIA23 = 2 x #pins  V congestion calculation Aspect ratio of net’s bounding box < 1 (H-BBOX: 2kN) Aspect ratio of net’s bounding box > 1 (V-BBOX: 3kN)

11 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Taxonomy of Via Modeling Approach (2) ③ Placement-based method  Inputs: placed design  accurate wirelength estimation  Baseline of #vias (V L )  Construct Steiner minimum tree (SMT)  Assign SMT segments to 1-tier routing layer u Horizontal  M3, Vertical segments  M2 u Diagonal segments  converted to ‘L’ shape  M2 and M3  Count #vias at each point  Average routing congestion  Large congestion requires more vias  Placement-based via count model S: Sum of SMT length T: Sum of available track length

12 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Model Fitting using Training Designs  Finding model coefficients  Initial guess:  : via count increase due to via blockages  ~ 4  : affects probability of via blockage   Final model coefficients ( )  Average 3.4% error Tech.Design#InstanceVLVL V est V actual Error (%) 65AES14,351113,530153,262154, JPEG63,932531,512591,788608, X5JPEG309,5432,626,9422,962,4003,028, AES18,078129,651179,439181, AES large-K10,99994,532128,441120, AES small-K31,074178,657196,410214, AES M515,468118,601178,190182, AES M615,468118,601168,940161, AES M715,468118,601167,542158, AES M815,468118,601160,819154, AES original pitch15,468118,601178,190182, AES half pitch15,468118,602145,139139, JPEG77,106588,776688,005695, X5JPEG349,2732,799,5533,226,7093,265, A via blockage can increase #vias by more than 4 Via blockage

13 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Model Accuracy on Industry Designs  We apply proposed placement-based via count model to designs from different technologies and different routers  Our model shows 8% error in average Tech.Design#instanceVLVL V est V actual Error (%) 45A39,247301,493354,206375, B119,369956,9571,153,8211,361, C194,6791,597,5281,873,3912,193, D160,5481,379,4721,587,5311,799, E145,7511,227,9111,648,9911,828, F538,8544,344,2935,818,9497,002, G43,629241,402277,201265, H134,157704,894789,101810, I265,7161,214,4481,341,7291,457, J240,1691,334,6641,460,1281,491, K159,197973,4421,174,3401,173, L185,816926,0431,159,1271,059, M576,3263,090,8073,512,1304,021, N463,9782,270,0452,587,2462,867, O598,0604,930,7535,442,9085,475, P31,132259,726323,594331,

14 of 14UCSD VLSI CAD Laboratory ISOCC-2008 Conclusion and Ongoing Work  Conclusion  We evaluate the sensitivities of design and technology parameters on via count  Propose a new accurate placement-based via count estimation model  Experimental results are promising  3.4% error on training designs with various instance counts, pins per gate, number of metal layers and wiring pitches  8% error on various industry designs from different technologies and routers  Ongoing work  Accurate wirelength estimation for analytical and netlist- based via count modeling  Feed into the development of improved routers  Ability to assess impact of varying design rules and/or different router runtime options