Cost-Effective Register File Soft Error reduction Pablo Montesinos, Wei Liu and Josep Torellas, University of Illinois at Urbana-Champaign.

Slides:



Advertisements
Similar presentations
Computer-System Structures Er.Harsimran Singh
Advertisements

Xavier Vera, Jaume Abella,Javier Carretero and Antonio Gonzalez.
1 Lecture 13: Cache and Virtual Memroy Review Cache optimization approaches, cache miss classification, Adapted from UCB CS252 S01.
IMPACT Second Generation EPIC Architecture Wen-mei Hwu IMPACT Second Generation EPIC Architecture Wen-mei Hwu Department of Electrical and Computer Engineering.
Performance of Cache Memory
ECE 2162 Tomasulo’s Algorithm. Implementing Dynamic Scheduling Tomasulo’s Algorithm –Used in IBM 360/91 (in the 60s) –Tracks when operands are available.
1 Saad Arrabi 2/24/2010 CS  Definition of soft errors  Motivation of the paper  Goals of this paper  ACE and un-ACE bits  Results  Conclusion.
School of Computing Exploiting Eager Register Release in a Redundantly Multi-threaded Processor Niti Madan Rajeev Balasubramonian University of Utah.
IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults Songjun Pan 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of.
Using Hardware Vulnerability Factors to Enhance AVF Analysis Vilas Sridharan RAS Architecture and Strategy AMD, Inc. International Symposium on Computer.
CS 7810 Lecture 25 DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design T. Austin Proceedings of MICRO-32 November 1999.
CPE 731 Advanced Computer Architecture ILP: Part II – Branch Prediction Dr. Gheith Abandah Adapted from the slides of Prof. David Patterson, University.
Chapter 12 Pipelining Strategies Performance Hazards.
Register Packing Exploiting Narrow-Width Operands for Reducing Register File Pressure Oguz Ergin*, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev Department.
Chapter 13 Reduced Instruction Set Computers (RISC) Pipelining.
Benefits of Early Cache Miss Determination Memik G., Reinman G., Mangione-Smith, W.H. Proceedings of High Performance Computer Architecture Pages: 307.
Virtual Memory and Paging J. Nelson Amaral. Large Data Sets Size of address space: – 32-bit machines: 2 32 = 4 GB – 64-bit machines: 2 64 = a huge number.
ISLPED’03 1 Reducing Reorder Buffer Complexity Through Selective Operand Caching *supported in part by DARPA through the PAC-C program and NSF Gurhan Kucuk,
Cost-Efficient Soft Error Protection for Embedded Microprocessors
ED 4 I: Error Detection by Diverse Data and Duplicated Instructions Greg Bronevetsky.
Memory: Virtual MemoryCSCE430/830 Memory Hierarchy: Virtual Memory CSCE430/830 Computer Architecture Lecturer: Prof. Hong Jiang Courtesy of Yifeng Zhu.
Lecture 8 Shelving in Superscalar Processors (Part 1)
An Intelligent Cache System with Hardware Prefetching for High Performance Jung-Hoon Lee; Seh-woong Jeong; Shin-Dug Kim; Weems, C.C. IEEE Transactions.
Checkpoint Based Recovery from Power Failures Christopher Sutardja Emil Stefanov.
Slipstream Processors by Pujan Joshi1 Pujan Joshi May 6 th, 2008 Slipstream Processors Improving both Performance and Fault Tolerance.
1 Multi-Level Error Detection Scheme based on Conditional DIVA-Style Verification Kevin Lacker and Huifang Qin CS252 Project Presentation 12/10/2003.
1/25 HIPEAC 2008 TurboROB TurboROB A Low Cost Checkpoint/Restore Accelerator Patrick Akl and Andreas Moshovos AENAO Research Group Department of Electrical.
Memory Management ◦ Operating Systems ◦ CS550. Paging and Segmentation  Non-contiguous memory allocation  Fragmentation is a serious problem with contiguous.
Efficient Software-Based Fault Isolation—sandboxing Presented by Carl Yao.
RAID Shuli Han COSC 573 Presentation.
1 Chapter 12 File Management Systems. 2 Systems Architecture Chapter 12.
Topics covered: Memory subsystem CSE243: Introduction to Computer Architecture and Hardware/Software Interface.
Three fundamental concepts in computer security: Reference Monitors: An access control concept that refers to an abstract machine that mediates all accesses.
Khaled A. Al-Utaibi  Interrupt-Driven I/O  Hardware Interrupts  Responding to Hardware Interrupts  INTR and NMI  Computing the.
CML CML Compiler-Managed Protection of Register Files for Energy-Efficient Soft Error Reduction Jongeun Lee, Aviral Shrivastava* Compiler Microarchitecture.
ReSlice: Selective Re-execution of Long-retired Misspeculated Instructions Using Forward Slicing Smruti R. Sarangi, Wei Liu, Josep Torrellas, Yuanyuan.
8.1 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Paging Physical address space of a process can be noncontiguous Avoids.
Yun-Chung Yang SimTag: Exploiting Tag Bits Similarity to Improve the Reliability of the Data Caches Jesung Kim, Soontae Kim, Yebin Lee 2010 DATE(The Design,
CS 211: Computer Architecture Lecture 6 Module 2 Exploiting Instruction Level Parallelism with Software Approaches Instructor: Morris Lancaster.
1 A Cost-effective Substantial- impact-filter Based Method to Tolerate Voltage Emergencies Songjun Pan 1,2, Yu Hu 1, Xing Hu 1,2, and Xiaowei Li 1 1 Key.
Relyzer: Exploiting Application-level Fault Equivalence to Analyze Application Resiliency to Transient Faults Siva Hari 1, Sarita Adve 1, Helia Naeimi.
Out-of-Order Commit Processors Adrián Cristal (UPC), Daniel Ortega (HP Labs), Josep Llosa (UPC) and Mateo Valero (UPC) HPCA-10, Madrid February th.
Modes of transfer in computer
Yun-Chung Yang TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array Shuai Wang; Jie Hu; Ziavras S.G; Dept. of Electr. & Comput.
Implicit-Storing and Redundant- Encoding-of-Attribute Information in Error-Correction-Codes Yiannakis Sazeides 1, Emre Ozer 2, Danny Kershaw 3, Panagiota.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
11 Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures Songjun Pan Yu Hu Xiaowei Li {pansongjun, huyu,
Reduction of Register File Power Consumption Approach: Value Lifetime Characteristics - Pradnyesh Gudadhe.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
Architectural Vulnerability Factor (AVF) Computation for Address-Based Structures Arijit Biswas, Paul Racunas, Shubu Mukherjee FACT Group, DEG, Intel Joel.
Methodology to Compute Architectural Vulnerability Factors Chris Weaver 1, 2 Shubhendu S. Mukherjee 1 Joel Emer 1 Steven K. Reinhardt 1, 2 Todd Austin.
Low-cost Program-level Detectors for Reducing Silent Data Corruptions Siva Hari †, Sarita Adve †, and Helia Naeimi ‡ † University of Illinois at Urbana-Champaign,
OOO Pipelines - III Smruti R. Sarangi Computer Science and Engineering, IIT Delhi.
Static Analysis to Mitigate Soft Errors in Register Files Jongeun Lee, Aviral Shrivastava Compiler Microarchitecture Lab Arizona State University, USA.
Reducing the Scheduling Critical Cycle using Wakeup Prediction HPCA-10 Todd Ehrhart and Sanjay Patel Center for Reliable and High-Performance Computing.
1 IP Routing table compaction and sampling schemes to enhance TCAM cache performance Author: Ruirui Guo, Jose G. Delgado-Frias Publisher: Journal of Systems.
1 Lecture: Out-of-order Processors Topics: branch predictor wrap-up, a basic out-of-order processor with issue queue, register renaming, and reorder buffer.
Spring 2008 CSE 591 Compilers for Embedded Systems Aviral Shrivastava Department of Computer Science and Engineering Arizona State University.
CS203 – Advanced Computer Architecture ILP and Speculation.
nZDC: A compiler technique for near-Zero silent Data Corruption
Smruti R. Sarangi Computer Science and Engineering, IIT Delhi
Page Replacement.
Lecture: Static ILP, Branch Prediction
Smruti R. Sarangi Computer Science and Engineering, IIT Delhi
Dynamic Prediction of Architectural Vulnerability
Dynamic Prediction of Architectural Vulnerability
Lecture: Static ILP Topics: predication, speculation (Sections C.5, 3.2)
Sampoorani, Sivakumar and Joshua
Fault Tolerant Systems in a Space Environment
Presentation transcript:

Cost-Effective Register File Soft Error reduction Pablo Montesinos, Wei Liu and Josep Torellas, University of Illinois at Urbana-Champaign

Overview  Study of register file vulnerability to SDC(Silent Data Corruption)  Shield – cost effective protection to register files  Highighting policies and techniques used in shield  Experiment - Results

Register File AVF  RF-AVF is the probability that a fault that occurs will lead to error.  Register lifetime is divided into PreWrite, Useful, and PostLastRead parts.  Based on AVF calculation we can divide lifetime of bit into ACE (Architecturally Correct Execution) and un-ACE cycles.

Register File AVF  During PreWrite Period – un-ACE  If used atleast once after write the reg switches to ACE state.  After last read on reg, switches back to un-ACE during PostLastRead

Highlighting Insights (1)  The combined %-USEFUL time of all registers is small

Highlighting Insights (1)  The average number of useful (live) registers is less than 20 (SPECint) and 17(SPECfp).  It is thus possible to redue the vulnerability of the register file by only protecting a subset of carefully chosen registers at a time.

Highlighting Insights (2)  Only a few long-lived registers contribute to overall Total useful time  On average less than 10% of register versions are long-lived.

Highlighting Insights (2)  On average 40% of useful time comes from the few long-lived versions.  In SPECfp, 5% of long-lived versions account for 46% of the useful time.

Motivation  Register files have a very high access rate.  High temperature thus leading to lesser Qcrit for the devices.  An error in an RF can propagate with hght failure probability  If we isolate a few register versions, predicting their life- time, and protect these register versions alone, high reliability can be achieved with limited overhead.

Shield - Architecture Life-Time Prediction Shielding Decision Register Error Check Error Recovery

Reg-Version Lifetime Prediction P12 => Used(1), Renamed(1) P7 => Used(0), Renamed(1)

Shielding Decision  These prediction bits are stored as status in the ECC table.  The decision to shield an incoming register version written is by: Availability of free ECC-Table entry Same register# present in the ECC table will be replaced with new entry. Existing reg-version with lesser lifetime than incoming reg- version will be replaced.  Replacement policy:

Register Error Check & Recovery  On a read request the register data is sent to the original datapath and shield.  If the Reg# matches with a tag entry, then the reg-data is checked for errors at the ECC-Checker.  If Error is detected Processor stalls the instruction I reading reg P Reg-data is corrected and written into RF Oldest read instruction reading reg P in ROB and all succeeding instructions is flushed. Processor resumes from flushed instruction.

Experiments- Results  AVF computation for RF with shield

Experiments-Results  AVF of intREG reduced by different replacement policies: LRU = 31% Effective = 63% OptEffective = 84% ( pinning of global pointers to particular ECC entries + Effective )  AVF for fpREG can be reduced maximum by 100%, because fewer fp-registers are in useful state.

Power and Area Impact  Shield only uses 3ECC generators and 3 ECC checkers.  Shield has 45% power overhead over a plain register file. (Full ECC has 2X)  Shield introduces an overall 10% area overhead.

Conclusion  A cost-effective architectural technique has been proposed to reduce the vulnerability of RF by 84%  The area and power overhead indicated is a marginal tradeoff for reliability achieved.