Design and Performance of the 6 GS/s Waveform Digitizing Chip DRS4 Stefan Ritt Paul Scherrer Institute, Switzerland at 40 mW per channel

Oct. 21st, 2008IEEE/NSS Dresden2 Switched Capacitor Array Cons No continuous acquisition No precise timing External (commercial) ADC needed Pros High speed (6 GHz) high resolution (11.5 bit resol.) High channel density (9 channels on 5x5 mm 2 ) Low power (10-40 mW / channel) Low cost (~ 10$ / channel) tt tt tt tt tt

Oct. 21st, 2008IEEE/NSS Dresden3 DRS4 Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm 2, radiation hard 8+1 ch. each 1024 cells Differential inputs, differential outputs Sampling speed 500 MHz … 6 GHz, PLL stabilized Readout speed 30 MHz, multiplexed or in parallel

Oct. 21st, 2008IEEE/NSS Dresden4 ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g MHz  3 us dead time (2.5 ns / 12 channels)

Oct. 21st, 2008IEEE/NSS Dresden5 Daisy-chaining of channels Channel 0 – 1024 cells Channel 1 – 1024 cells Channel 2 – 1024 cells Channel 3 – 1024 cells Channel 4 – 1024 cells Channel 5 – 1024 cells Channel 6 – 1024 cells Channel 7 – 1024 cells Domino Wave Generation Deeper Sampling Depth can be reached by multiplexing channels

Oct. 21st, 2008IEEE/NSS Dresden6 Daisy-chaining of channels Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input

Oct. 21st, 2008IEEE/NSS Dresden7 Single Channel Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 0 clock Channel 0Channel 1 1 Channel 2 1 Channel 3 1 Channel 4 1 Channel 5 1 Channel 6 1 Channel 7 1 DRS4 Connect channels externally to keep high bandwidth limited by bond wires (PCB or analog switches) DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells

Oct. 21st, 2008IEEE/NSS Dresden8 Chip Daisy Chaining DRS4 SROUT SRIN DRS4 SROUT SRIN DRS4 SROUT SRIN Virtually unlimited sampling depth

Oct. 21st, 2008IEEE/NSS Dresden9 Simultaneous Write/Read Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 FPGA Channel 0Channel 1 1 Channel 0 readout 8-fold analog multi-event buffer Channel 2 1 Channel 1 0 Expected crosstalk ~few mV

Oct. 21st, 2008IEEE/NSS Dresden10 Trigger an DAQ on same board Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (6 GHz samples) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus “Free” local trigger capability without additional hardware

DRS4 Test Results

Oct. 21st, 2008IEEE/NSS Dresden12 On-chip PLL Reference Clock f clk = f samp / 2048 V speed PLL jitter « 100 ps (Spartan-3 jitter 150 ps) “Dead Band” free Does not lock on higher harmonics PLL jitter « 100 ps (Spartan-3 jitter 150 ps) “Dead Band” free Does not lock on higher harmonics loop filter DRS4 Simulation Measurement Phase detector up down

Oct. 21st, 2008IEEE/NSS Dresden13 Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) 850 MHz (-3dB) QFP package final bus width Simulation Measurement

Oct. 21st, 2008IEEE/NSS Dresden14 Timing jitter t1t1 t2t2 t3t3 t4t4 t5t5 Inverter chain has transistor variations   t i between samples differ  “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i =  t i –  t nominal “Integral temporal nonlinearity” TI i =  t i – i  t nominal “Random aperture jitter” = variation of  t i between measurements Inverter chain has transistor variations   t i between samples differ  “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i =  t i –  t nominal “Integral temporal nonlinearity” TI i =  t i – i  t nominal “Random aperture jitter” = variation of  t i between measurements TD 1 TI 5

Oct. 21st, 2008IEEE/NSS Dresden15 Fixed jitter calibration Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis

Oct. 21st, 2008IEEE/NSS Dresden16 Fixed Pattern Jitter Results TD i typically ~50 ps 5 GHz TI i goes up to ~600 ps Inter-channel variation on same chip is very small since all channels are driven by the same domino wave

Oct. 21st, 2008IEEE/NSS Dresden17 Random Jitter Results Sine curve frequency fitted for each measurement (PLL jitter compensation) Encouraging result for DRS3: 2.7 ps RMS (best channel) 3.9 ps RMS (worst channel) Differential measurement t1 – t2 adds a  2, needs to be verified by measurement Measurement of n points on a rising edge of a signal improves by  n Sine curve frequency fitted for each measurement (PLL jitter compensation) Encouraging result for DRS3: 2.7 ps RMS (best channel) 3.9 ps RMS (worst channel) Differential measurement t1 – t2 adds a  2, needs to be verified by measurement Measurement of n points on a rising edge of a signal improves by  n Measurements for DRS4 currently going on, expected to be slightly better

Oct. 21st, 2008IEEE/NSS Dresden18 Experiments using DRS chip MAGIC-II 1200 channels DRS2 MEG 3000 channels DRS2 BPM for 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned)

Oct. 21st, 2008IEEE/NSS Dresden19 Availability DRS4 will become available in larger quantities in November 2008 Chip can be obtained from PSI on a “non-profit” basis Delivery “as-is” Reference design (schematics) from PSI Costs ~ 10-15$/channel VME boards from industry in channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 6 GHz 64-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 6 GHz Input USB 2.0 ext. Trigger DRS4

Oct. 21st, 2008IEEE/NSS Dresden20 Conclusions Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future DRS4 chip solves all known issues of DRS3 and adds more flexibility DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 3 ps timing resolution ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this technology

Oct. 21st, 2008IEEE/NSS Dresden22 A bit of history… DRS2 DRS3 DRS1 MEG Experiment searching for  e  down to MEG Experiment searching for  e  down to DRS Channels with GHz sampling 3000 Channels with GHz sampling

Oct. 21st, 2008IEEE/NSS Dresden23 DRS4 packaging DRS3 DRS4 9 mm 18 mm 4.2 mm DRS4 flip-chip

Oct. 21st, 2008IEEE/NSS Dresden24 “Residual charge” problem R “Ghost pulse” 2 GHz “Ghost pulse” 2 GHz After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses Solution: Clear before write write clear Implemented in DRS4 Implemented in DRS4

Oct. 21st, 2008IEEE/NSS Dresden25 Sine Curve Fit Method S. Lehner, B. Keil, PSI i j y ji : i-th sample of measurement j a j f j  j o j : sine wave parameters  i : phase error  fixed jitter “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine  i using all measurements where sample “i” is near zero crossing Make several iterations “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine  i using all measurements where sample “i” is near zero crossing Make several iterations

Oct. 21st, 2008IEEE/NSS Dresden26 Signal-to-noise ratio (DRS3!) “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) Offset Correction

Oct. 21st, 2008IEEE/NSS Dresden27 Global Timing Clock signal 20 MHz Reference clock PMT hit Domino stops after trigger latency 8 inputs shift register Reference clock domino wave MUX PLL jitter O(100ps)  Timing difference between signals sampled by different chips need a global reference clock

Oct. 21st, 2008IEEE/NSS Dresden28 Datasheet

Oct. 21st, 2008IEEE/NSS Dresden29 Interleaved sampling delays (200ps/8 = 25ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 6 GSPS * 8 = 48 GSPS Possible with DRS4 if delay is implemented on PCB

Oct. 21st, 2008IEEE/NSS Dresden30 Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS4 Bandwidth (-3db) 300 MHz> 1000 MHz950 MHz Sampling frequency 1 or 2 GHz10 MHz … 3.5 GHz500 MHz … 6 GHz Full scale range ±0.5 V+0.4 …2.1 V+0.1 … 1.1V Effective #bits 12 bit10 bit12 bit Sample points 1 x x 2569 x 1024 Channel per board 4N/A64 Digitization 5 MHzN/A30 MHz Readout dead time 650  s150  s3  s – 370  s Integral nonlinearity ± 0.1 % ± 0.05% Radiation hard No Yes (chip) Board V1729 (CAEN)-planned (CAEN)

Oct. 21st, 2008IEEE/NSS Dresden31 On-line waveform display click template fit pedestal histo  848 PMTs “virtual oscilloscope”

Oct. 21st, 2008IEEE/NSS Dresden32 Latch Constant Fraction Discr. Latch 12 bit Clock  + + MULT Latch 00 & <0 Delayed signal Inverted signal Sum