Dec. 29, 2005Texas Instruments (India)1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA For more details, see Vishwani D. Agrawal, Alok S. Doshi,

Dec. 29, 2005Texas Instruments (India)2 Problem Statement To find the smallest test set to detect all single stuck-at faults in a combinational circuit. An existing solution: –Group faults into fault sets using fault independence –Generate concurrent tests for each group Contribution of this paper: Devise a simulation- based implementation for this solution.

Dec. 29, 2005Texas Instruments (India)3 Outline Introduction Simulation-based Independence Fault Collapsing Simulation-based Concurrent Test Generation Results Conclusions

Dec. 29, 2005Texas Instruments (India)4 Introduction v1v1 v2v2 v3v3... T(F1) T(F2) Problem of finding a minimal test: Static compaction cannot guarantee optimality. Dynamic compaction is complex. Solution: Target both faults F1 and F2 at the same time to find a single test. We define this as concurrent test generation. Test set for fault F1 Test set for fault F2

Dec. 29, 2005Texas Instruments (India)5 Fault Classification F1 and F2 are equivalent. F1 dominates F2. F1 and F2 are independent. F1 and F2 are concurrently testable. T(F1) = T(F2) T(F1) T(F2) T(F1) T(F2) T(F1)

Dec. 29, 2005Texas Instruments (India)6 Definitions Independent Faults 4 : Two faults are independent if and only if they cannot be detected by the same test vector. Concurrently-Testable Faults: Two faults that neither have a dominance relationship nor are independent, are defined as concurrently-testable faults. 4 S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the role of Independent Fault Sets in the Generation of Minimal Test Sets,” in Proc. International Test Conf., 1987, pp

Dec. 29, 2005Texas Instruments (India)7 Structural Independences sa1 sa0 sa1 Functional Independences: Found by ATPG-like methods.

Dec. 29, 2005Texas Instruments (India)8 Example Circuit a b c d e x y C17 - ISCAS85 Benchmark Circuit 1 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp All faults are Stuck-at-1 type

Dec. 29, 2005Texas Instruments (India)9 Independence Matrix and Graph C17 - ISCAS85 Benchmark Circuit F Clique

Dec. 29, 2005Texas Instruments (India)10 Independence Fault Collapsing 1,8 5,11,7 3,9,2 4,6,10 2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9 th VLSI Design and Test Symp., Aug. 2005, pp C17 - ISCAS85 Benchmark Circuit A “similarity” based algorithm [2] collapses the independence graph: Highly Similar Highly Dissimilar Equiv.Indep. Similarity of a fault-pair

Dec. 29, 2005Texas Instruments (India)11 Simulation-based Independence Fault Collapsing 2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9 th VLSI Design and Test Symp., Aug. 2005, pp The independence graph generation procedure [2] requires ATPG. Here we present a new method for graph generation using simulation: –Start with a fully-connected independence graph for an equivalence collapsed fault set. –Simulation of random vectors without fault dropping removes edges between faults detected by the same vector.

Dec. 29, 2005Texas Instruments (India)12 Simulation-based Independence Fault Collapsing bit ALU 301

Dec. 29, 2005Texas Instruments (India)13 Simulation-based Concurrent Test Generation For each group, generate all test vectors for the first fault in the group. –If the number of test vectors for a fault is large, use a subset (e.g., 250 maximum) of vectors. Simulate all faults in the group to select one vector that detects most faults in that group. –If more vectors than one detect the same number of faults within the group, then select the vector that detects most faults outside the group as well.

Dec. 29, 2005Texas Instruments (India) bit ALU Result Group numberNumber of faults in groupConcurrent test vector All 56 faults detected by eleven previously generated vectors

Dec. 29, 2005Texas Instruments (India)15 * Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000 Results Circuit No. of concurrent groups Concurrent ATPG Single-fault ATPG VectorsCPU s* AtalantaBest known VectorsCPU s*VectorsCPU s*** 1-b adder 2-b adder 4-b adder 8-b adder 16-b adder 32-b adder 4-b ALU c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c ** 52** 16** 84** 106** 44** 84** 37** 12** 73**

Dec. 29, 2005Texas Instruments (India)16 Number of Vectors for Increasing Circuit Sizes (100% Stuck-at Coverage) Single-fault ATPG (no compaction) Concurrent ATPG Minimum achieved! (dynamic compaction)

Dec. 29, 2005Texas Instruments (India)17 CPU Seconds for Increasing Circuit Sizes (100% Stuck-at Fault Coverage) Concurrent ATPG Minimum achieved! (dynamic compaction)

Dec. 29, 2005Texas Instruments (India)18 Conclusion Concurrent test generation produces compact tests when combined with independence fault collapsing. ATPG and set covering problems have exponential time complexities. Hence, we cannot expect absolute optimality for large circuits. The concurrent ATPG procedure of this paper gives significantly smaller, and sometimes the optimum, test sets. There is scope for improving the simulation-based algorithms for independence fault collapsing and concurrent test generation.

Dec. 29, 2005Texas Instruments (India)19 Thank You!