Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 6 - ASIC Design September 9, 2002

ECE 425 Spring 2005Lecture 6 - ASIC Design2 Announcements  Homework due Friday 2/18:  2-2, 2-5, 2-6, 2-7, 2-8, 2-9, 2-12, 2-13, 2-20  Problem 2-13 hints: Assume VDD / p-transistors in top half, Gnd / n-transistors in bottom half  Entrance Exam due Friday 2/18  Reading  Wolf ,  Engineering Recruiting Day: Fri. 4/1 in Philadelphia  Submit resumes to Career Services by Feburary 25

ECE 425 Spring 2005Lecture 6 - ASIC Design3 Where we are...  Last Time:  Layout  Scaling  Today:  The ITRS Roadmap  Overview of Layout-Level Tools  ASIC Design

ECE 425 Spring 2005Lecture 6 - ASIC Design4 Predicting future scaling - the ITRS  ITRS = International Technology Roadmap for Semiconductors  Sponsored by Semiconductor Industry Association  Goal: Forecast challenges in coming technology nodes  Overview: W&H Table 4.17

ECE 425 Spring 2005Lecture 6 - ASIC Design5 Review: VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections

ECE 425 Spring 2005Lecture 6 - ASIC Design6 Levels of Abstraction - Perspective  Right now, we’re focusing on the “low level”:  Circuit level - transistors, wires, parasitics  Layout level - mask objects  We’ll work upward to higher levels:  Logic level - individual gates, latches, flip-flops  Register- transfer level  Behavior level - specifications

ECE 425 Spring 2005Lecture 6 - ASIC Design7 The Challenge of Design  Start: higher level (specification)  Finish: lower level (implementation)  Must meet design criteria and constraints  Design time - how long did it take to ship a product?  Performance - how fast is the clock?  Cost - NRE + unit cost doing this successfully requires verification!

ECE 425 Spring 2005Lecture 6 - ASIC Design8 Layout-Level Design Tools  Design Tools  Schematic Editor (SUE)  Layout Editor (MAGIC)  Analysis & Verification Tools  Circuit Extractor (MAGIC)  Circuit Simulator (Spice)  Timing Simulator (IRSIM)  Timing Analyzer  Layout vs. Schematic (LVS) Equivalence Checker (gemini)

ECE 425 Spring 2005Lecture 6 - ASIC Design9 CAD Tool Survey: Layout Design  Layout Editors  Design Rule Checkers (DRC)  Circuit Extractors  Layout vs. Schematic (LVS) Comparators  Automatic Layout Tools  Layout Generators  ASIC: Place/Route for Standard Cells, Gate Arrays

ECE 425 Spring 2005Lecture 6 - ASIC Design10 Layout Editors  Goal: produce mask patterns for fabrication  Grid type:  Absolute grid (MAX, LASI, LEdit, Mentor ICStation, other commercial tools)  Magic: lambda-based grid - easier to learn, but less powerful  Mask description:  Absolute mask (one layer for each mask)  Magic: symbolic masks (layers combine to generate actual mask patterns)

ECE 425 Spring 2005Lecture 6 - ASIC Design11 Design Rule Checkers  Goal: identify design rule violations  Often a separate tool (built in to Magic)  General approach: “scanline” algorithm  Computationally intensive, especially for large chips

ECE 425 Spring 2005Lecture 6 - ASIC Design12 Circuit Extractors  Goal: extract netlist of equivalent circuit  Identify active components  Identify parasitic components Capacitors Resistors

ECE 425 Spring 2005Lecture 6 - ASIC Design13 Layout Versus Schematic (LVS)  Goal: Compare layout, schematic netlists  Compare transistors, connections (ignore parasitics)  Issue error if two netlists are not equivalent  Important for large designs

ECE 425 Spring 2005Lecture 6 - ASIC Design14 Automatic Layout Tools  Layout Generators - produce cell from spec.  Simple: Procedural specification of layout (see book Fig. 2-35, p. 100)  Complex: Netlist - places & wires individual transistors  Common generators: Memory (RAM/ROM) Structured Logic (PLA)  ASIC - Place, route modules with fixed shape  Standard Cells - use predefined cells as "cookie cutters"  Gate Arrays - configurable pre-manufactured gates (only change metal masks)  FPGAs - electrically configurable array of gates

ECE 425 Spring 2005Lecture 6 - ASIC Design15 ASICs - Application-Specific ICs  Standard Cells  Gate Arrays  Field-Programmable Gate Arrays

ECE 425 Spring 2005Lecture 6 - ASIC Design16 Standard Cells  All cells a fixed height (variable width)  Provide Vdd, Gnd to lines to connect by abutment, overlap  Cells placed in rows by placement program  Cells connected in channels by channel router

ECE 425 Spring 2005Lecture 6 - ASIC Design17 Standard Cell Layout  Multiple metal layers allow over-the-cell routing  Channels shrink or vanish in this case

ECE 425 Spring 2005Lecture 6 - ASIC Design18 Standard Cell Detail

ECE 425 Spring 2005Lecture 6 - ASIC Design19 “Sea of Gates”  Completed array of gates without final metal  Metal specified by CAD Tools  Tradeoffs vs standard cells  faster turnaround  lower NRE (non-recurring engineering) cost  higher unit cost Gate Arrays V DD Gnd

ECE 425 Spring 2005Lecture 6 - ASIC Design20 Field-Programmable Gate Arrays (FPGAs)  Fixed array of gates  Electrically programmable interconnect  Tradeoffs: very low NRE, high unit cost CLB

ECE 425 Spring 2005Lecture 6 - ASIC Design21 ASIC Tradeoffs

ECE 425 Spring 2005Lecture 6 - ASIC Design22 ASIC Economics  Non-recurring Engineering (NRE) cost - up-front cost of setting up manufacturing  Unit cost - cost of each chip once production begins Total Cost Volume Custom Std. Cell Gate Array FPGA

ECE 425 Spring 2005Lecture 6 - ASIC Design23 ASIC Trends - FPGAs vs. ASICs  Standard cell NRE costs are rising rapidly  FPGAs improving in size, performance, cost  Will FPGAs supplant ASICs? Total Cost Volume Std. Cell (current) FPGA (current) Break-Event Point FPGA (future) Std. Cell (future)

ECE 425 Spring 2005Lecture 6 - ASIC Design24 ASIC Trends - Perspectives  The ASIC has been declared “dead”  Rationale: NRE costs are high, FPGAs more cost-effective in all but high-volume cases  This argument is very popular with FPGA vendors  But, reports may be exaggerated!  Many chips still designed with standard cells  Current trend: ASICs with IP blocks  Current trend: structured ASICs

ECE 425 Spring 2005Lecture 6 - ASIC Design25 Design with Intellectual Property (IP)  Key Idea: re-use predesigned components  Hard IP - predesigned layout in a specific technology Standard Cells Processor Cores Memory Cores  Soft IP - synthesizeable HDL Proprietary algorithms (e.g. MPEG encoding/decoding)

ECE 425 Spring 2005Lecture 6 - ASIC Design26 Structured ASICs  Key idea: provide a platform with many (but not all) functions for a common application  Network/Telecomm: microprocessor, DSP, serializer/deserializer  Embedded Systems: microcontroller, smart timer, other peripherals  Allow user to customize part of design to add “secret sauce”  FPGA Fabric - program in field  Gate Array or “Gate Array Like” - customize with metal layers only  Important benefit: lower NRE costs

ECE 425 Spring 2005Lecture 6 - ASIC Design27 Structured ASIC eaxmple:  LSI Logic RapidChip Platform (EE Times 9/9/02)  Application-specific “hard IP” on pre-designed, pre- manufactured chip  Logic added by adding metal layers to customize (maybe gate arrays aren’t dead after all?)

ECE 425 Spring 2005Lecture 6 - ASIC Design28 About Lab 4  Extraction using Magic  Simulation with IRSIM  Switch-Level Simulator  RC (  ) timing model  LVS using gemini

ECE 425 Spring 2005Lecture 6 - ASIC Design29 Lab 4 - Extraction  in magic - :extract creates filename.ext  in shell - ext2sim filename creates filename.sim

ECE 425 Spring 2005Lecture 6 - ASIC Design30 Lab 4 - Simulation using IRSIM  Starting IRSIM in shell - irsim ami.prm filename.sim  Node values in simulation: 0, 1, X,...  Some important commands analyzer net1 net2 …trace signals in waveform h netset net to logic H l netset net to logic L vector vname net1 net2 …group nets into “bus” set vname 001…set bus to value s timestep simulation - time filenameinclude command file qquit simulation

ECE 425 Spring 2005Lecture 6 - ASIC Design31 Lab 4 - LVS using Gemini  Starting IRSIM in shell - gemini file1.sim file2.sim  Where to get the files?  file1.sim - generated by Sue “sim it”  file2.sim - generated by :extract, ext2sim

ECE 425 Spring 2005Lecture 6 - ASIC Design32 Coming Up:  Combinational Logic Design  Gate Design & Layout  Delay  Noise Margin  Power Consumption  A Mixed-Signal Digression: D/A Converters