Energy Efficient and High Speed On-Chip Ternary Bus Chunjie Duan Mitsubishi Electric Research Labs, Cambridge, MA, USA Sunil P. Khatri Texas A&M University, College Station, TX, USA

03/13/ Motivation Trends in VLSI design –Shrinking feature size Deep SubMicron (DSM) and Very Deep SubMicron (VDSM) processes –Scaling down supply voltage –Increasing die-size (e.g. SoC, NoC, CMP) Impacts Smaller gate delay (high speed logic) Lower switching power per gate High complexity (>billion gates) χIncreasing power consumption χHigher leakage current (standby power) χReduced noise margin χIncreasing interconnect delay Interconnect delay >> gate delay Global interconnect becomes the performance bottleneck

03/13/ On-chip Bus Interconnects The impact of DSM / VDSM: –W↓, P↓ – L↑, T↑ to avoid quadratic increase in resistance of the wire: Inter-wire capacitance C I is much greater than substrate capacitance C L, → crosstalk becomes dominant – λ = C I / C L > 10 for metal 4 in a  m CMOS process CLCL CLCL CLCL T W CICI CICI CICI CICI CLCL CLCL CLCL Earlier process P DSM process

03/13/ Ternary Bus and Mapping Advantage of a ternary bus –low voltage step: V dd/2 instead of V dd We propose a bit-to-bit binary-ternary mapping scheme –Each binary bit is mapped directly to a line on the ternary bus. –A binary 0 is mapped to a middle value on the ternary bus. i.e. 0 b ->0 t. –A binary 1 is mapped to either high or low value on the ternary bus. i.e. 1 b  + or 1 b  -. Disadvantage: lower bit density (1 bit/line vs 1.58 bit/line for true ternary bus) Advantages: direct mapping and flexible polarity –Ternary to binary conversion is very slow and complex –Flexible polarity results in low crosstalk. e.g., the ternary vectors +0+, -0-, +0- and -0+ all represent the same binary value 101. Each ternary value is represented by the polarity P j and the magnitude D j Ternary driver truth table DjDj PjPj TjTj Vout 0X0V0V0 10-V- 11+V+V+

03/13/ Crosstalk in a Multi-valued Bus Define the effective crosstalk as –where  j,k = sgn(  j )  V k is the normalized voltage change, and. NOL is the number of logic levels Delay can be approximated as –for  Energy consumption is –when  >> 1, For ternary bus, V step = V dd /2, we know –max(X eff,j )= 8 –min(X eff,j )=0 Bus speed/power is highly data pattern dependent! Table 1. Examples of Total Crosstalk V t-1 VtVt X eff

03/13/ A Low Power, High Speed 4X Ternary Bus Using direct bit-to-bit mapping Coding rules: –Rule #1: A direct - ↔ + transition is prohibited. –Rule #2: A 1 b  0 b is mapped as - t  0 t or + t  0 t depending only on the current polarity of the 1 b. –Rule #3: For a 0 b  1 b transition on b j, if b j-1 is transitioning, P j is coded so both lines transition in the same direction. –Rule #4: For a 0 b  1 b transition on b j, if b j-1 is not transitioning and and b j+1 is transitioning from 1 to 0, P j is coded so that the j th and (j+1) th line transition in the same direction. –Rule #5: For a 0 b  1 b transition on b j, if no transition on either neighbor, P j is coded so {P j = P j-1 or P j = P j+1 } with P j = P j-1 having the higher priority. The 1 st rule guarantees max(X eff,j ) = 4, therefore a 2X speed up from a conventional binary bus The other rules are designed to lower the probability of high value X eff,j ’s occurrence on the bus Identical encoder/decoder logic for each bit An example of 4X ternary sequences BinaryTernaryX eff —

03/13/ An Even Faster 3X Ternary Bus Partition the bus into 5-bit groups Insert shield wire between groups Apply the same rules for 4X bus It can be proven that such a configuration guarantees max(X eff ) = 3 –Additional 33% speed up over 4X ternary bus At the cost of 20% additional wires 4X bus encoder and driver circuit 3X bus encoder and driver circuit

03/13/ Circuit Implementations Encoder implemented based on the 5 rules Decoder is extremely simple (implemented with two 2-input gates) Ternary driver and receiver can be implemented in current or voltage mode –Current mode is more power hungry (static current) –Voltage mode requires a low impedance Vdd/2 supply M1 M3 M2 V dd V /2 bus w xtalk I r e f V dd I ref 2 I r e f out2 1 d I-receiver ENCd in M3 M4 M5 M1 M2 I-driver to D j+1 j-1 C L C I R bus to D j+1 j-1 C L C I R ENC din V dd V ref1 V 2 V dd V V ref2 V 1 d out V-driver V-receiver shared V-ref (B)Voltage mode (A)current mode

03/13/ Experimental Results Crosstalk distribution and normalized energy consumption comparison (code ternary vs. half-swing binary) Bus Size 0X1X2X3X4XEF (x10 4 ) % 5B T B T B T B T The power saving comes from the redistribution of the X eff –More transitions are pushed towards lower X eff The average power saving is ~27% 4X: ternary bus using 4X code; HB: half-swing binary bus; RP: ternary bus with random polarity; TT: true ternary bus

03/13/ Experimental Results The proposed 4X and 3X busses are advantageous over other bus coding schemes. EF: Normalized total energy PDP: power delay product Bus type4XT3XTSBHBRPTT EF ( x10 4 ) Delay4x3x4x 8x PDP ( x10 5 ) Pwr saving (%) PDP gain (%) Bus Area XT: ternary bus using 4X code; 3XT: ternary bus with 3X code; SB: binary bus with shielding; HB: half-swing binary bus; RP: ternary bus with random polarity; TT: true ternary bus Bus performance comparison

03/13/ Experimental Results Eye diagrams for uncoded an coded busses (10mm)

03/13/ Summary Crosstalk classification was extended to multi-valued buses We proposed a direct bit-to-bit binary-ternary mapping scheme which results in a simple CODEC design. We proposed a 4X coding scheme that allows us to double the speed of a conventional ternary bus and save energy. We proposed a coding scheme (3X coding) to attain an additional 33% speed gain at the cost of 20% area overhead. We designed and implemented the CODEC and ternary driver/receiver. Our experimental results show significant power saving (27%) and speed gain (2X or more) over other schemes