CMOL overview ● CMOS / nanowire / MOLecular hybrids ● Uses combination of Micro – Nano – Nano implements regular blocks (ie memory) – CMOS used for logic, decoder and driver circuits ● Best suited for memories and cell-based FPGA design

Potential Advantages of CMOL ● FPGAs are easier to design – Doesn't face the “design bottleneck” of custom hardware design ● regular structures for memory applications ● CrossNets for neural networks

Potential Drawbacks to CMOL ● Sub-optimal for specific tasks (datapath) ● No nano latches – uses CMOS registers – Very little pipelining due to high register cost – Contrasts NASICs dynamic style ● 2 step configuration relies heavily on (unreliable) interaction with CMOS – Map design onto CMOL fabric – Detect errors and reconfigure as needed

CMOL concerns ● CAD tools undeveloped ● Parasitic interactions between collocated nano and micro devices? ● Power density issues?

Conclusion ● CMOL offers an efficient method for possible implementation of designs of identical configurable cells like memories and FPGAs ● Such designs are not well suited for all tasks ● CMOL argues that the incremental improvement of NASICs would not be worth design cost – However, industry does pay great cost for incremental improvement all the time ● Unless there is a shift in the way we compute, CMOL will not be optimal for logic

Outlook ● FPGA style circuits and memories might be among the first circuits to use nano devices ● Even if they are, NASICs will still be needed for optimized logic circuits