Verification & Test CISS – Aalborg Brian Nielsen Kim Guldstrand Larsen Arne Skou

ARTIST2 NoE, Test & Verification Meeting 1 2 Overview zCISS zVerification & Scheduling yS/E-machines, UML & visualSTATE yTimed Automata & UPPAAL yPriced Timed Automata & UPPAAL CORA yMarkov Decision Processes & RAPTURE zTesting yConnectivety Testing yOn-line Testing & UPPAAL TRON yGateHouse, Generic Test Adaptation yvisualSTATE Test Extensions

ARTIST2 NoE, Test & Verification Meeting 1 3 BRICS Machine Basic Research in Computer Science, MEuro 100 Aalborg Aarhus Tools

ARTIST2 NoE, Test & Verification Meeting 1 4 CISS Center for Embedded Software Systems, 2002 – Institute for Computer Scienc Institute for Computer Scienc Institute for Elektronic Systemer Institute for Elektronic Systemer Modelling and Validation; Programming Languages; Software Engineering Modelling and Validation; Programming Languages; Software Engineering Embedded Systems Communication; HW/SW Power Management Embedded Systems Communication; HW/SW Power Management Distributed Real Time Systems Control Theory; Real Time Systems; Networking. Distributed Real Time Systems Control Theory; Real Time Systems; Networking. ICT Companies External collaboration: EE&CS Berkeley Twente U Uppsala U AMETIST ARTIST NASA Ames External collaboration: EE&CS Berkeley Twente U Uppsala U AMETIST ARTIST NASA Ames MVTU 25.5 MDKK MVTU 25.5 MDKK Regional & City Councils 12 MDKK Regional & City Councils 12 MDKK Aalb. Uni MDKK Aalb. Uni MDKK Companies MDKK Companies MDKK 20 Staff / 12 PhD studens

ARTIST2 NoE, Test & Verification Meeting 1 5 Focus Areas Applikationer Teknologi Værktøj Modeller Metoder Protokoller Design- og Prog.sprog Operativ system HW platform GPS Open source Home automation Mobile robotter Intelligente sensorer Ad hoc netværk Mobiltlf Audio/Video Konsum elektr Kontrolsystemer Automobile X-by wire Algoritmik SW-udvikling Effektforbrug Pålidelighed Test & Validering Hybride systemer Kommunikationsteori Model Based Development of Embedded Software Intelligent Sensor Networks Embedded & RT Platform LAB Safety Critical Software Systems Embedded System Testing & Verification HW/SW Co-Design, Design Space Exploration Resource Optimal Scheduling

ARTIST2 NoE, Test & Verification Meeting 1 6 visualSTATE zUML compatible development tool zAutomatic code-generation zCheck for generic properties. zPatented CBR technique developed in 1998 [TACAS98, TACAS99] zNew project: yExtension of visualSTATE w test-case generation facilities yContext dependent code- generation [FASE05] yImprovement of verification engine (handling of signal- queue).

ARTIST2 NoE, Test & Verification Meeting 1 7 UPPAAL

ARTIST2 NoE, Test & Verification Meeting 1 8 Modus Operandi IDEA e.g. language extension datastructure abstraction algorithm … Theoretical development & validation Prototype implementation & performance evaluation In-house evaluataion Incorporation in official release

ARTIST2 NoE, Test & Verification Meeting 1 9 Issues zDatastructures for Passed and Waiting zDatastructures for zones zDo we really need to always store in Passed ? zDo we really need to add all successors ? zWhich symbolic state to select from Waiting ?

ARTIST2 NoE, Test & Verification Meeting 1 10 Passed/Waiting Hash table States Hash table [SPIN03] PASSED WAITING

ARTIST2 NoE, Test & Verification Meeting 1 11 Passed/Waiting Hash table States PASSED Hash table WAITING Hash table States UNIFIED Waiting queue [SPIN03]

ARTIST2 NoE, Test & Verification Meeting 1 12 Passed/Waiting Hash table States PASSED Hash table Hash table States UNIFIED Waiting queue [SPIN03]

ARTIST2 NoE, Test & Verification Meeting 1 13 To-store-or-not 117 states total ! 81 states entrypoint ! 9 states [CAV03]

ARTIST2 NoE, Test & Verification Meeting 1 14 Datastructures for Zones zDBMs zMinimal Constraint Form zCDDs x1x2 x3x UPPAAL library to be made available Alexandre David

ARTIST2 NoE, Test & Verification Meeting 1 15 Zone Abstractions  Abstraction taking maximum constant into account necessary for termination  Utilization of distinction between lower and upper bounds  Utilization of location-dependency [TACAS03,TACAS04]

ARTIST2 NoE, Test & Verification Meeting 1 16 LU Abstraction THEOREM For any state in the LU- abstraction there is a state in the original set simulating it  LU abstraction is exact wrt reachability [TACAS04]

ARTIST2 NoE, Test & Verification Meeting 1 17 Zone abstractions ClassicalLoc. dep. MaxLoc. dep. LUConvex Hull

ARTIST2 NoE, Test & Verification Meeting 1 18 Symmetry Reduction zExploitation of full symmetry may give factorial reduction zMany timed systems are inherently symmetric zComputation of canonical state representative using swaps. [Formats 2003]

ARTIST2 NoE, Test & Verification Meeting 1 19 Symmetry Reduction [Formats 2003]

ARTIST2 NoE, Test & Verification Meeting 1 20 Analysis Methods Identified zTechniques identified and implemented: yZone abstractions (max constant, loc.dep., lower/upper bounds) yStorage techniques ySymmetry reduction yCost-guiding search and pruning yDistributed exploration yCycle acceleration ySweep line reduction zConclusion:“ Progress by far exceeding expectations ” zFuture: “ Consolitation & combination ”

ARTIST2 NoE, Test & Verification Meeting 1 21 UPPAAL CORA

ARTIST2 NoE, Test & Verification Meeting 1 22 UPPAAL CORA zBranch of UPPAAL with support for cost- optimal reachability. zBased on priced zones zSubstantial performance improvement by translation to min-cost-flow problems zCompetitive with MILP zPossibility of guiding (improving) search by heur and remaining meta-variable. zFully compatible w UPPAAL (GUI). zApplication to AXXOM case-study. zApplication to vehicle routing problems w time-windows (Carmen Consulting). zApplied to Dynamic Voltage Scheduling, WCET analysis. zVisualization of generated optimal schedules using Gantt charts (to be finished during beginning of 2005). zNew optimization problems to be added: yOptimal Infinite schedules [HSCC’04] yConditional Optimal Schedules [FOSSACS’05] x · 2 x ¸ 4 x ¸ 3 x ¸ 4 x ¸ 5 y:=0 y=0 x:=0 c’=5 c’=1 c´=10 c+=1 c+=7 AB C C G Priced Timed Automata [HSCC’01, CAV’01, EMSOFT’03, TACAS’04]  = (A x=y=0) ! 0 (B x=y=0) ! 0 (C x=y=0) ! 5,5 (C x=y=5) ! 1 G

ARTIST2 NoE, Test & Verification Meeting 1 23 cost t E LT E earliest landing time T target time L latest time e cost rate for being early l cost rate for being late d fixed cost for being late e*(T-t) d+l*(t-T) Planes have to keep separation distance to avoid turbulences caused by preceding planes Runway Aircraft Landing

ARTIST2 NoE, Test & Verification Meeting 1 24 UPPAAL CORA PTA versus MILP on Aircraft Landing Benchmark DEC300/700 (225MHz) vs Pentium MMX (200 MHz) Source: Baesley et al’2000

ARTIST2 NoE, Test & Verification Meeting 1 25 RAPTURE Probabilistic Reachability for Markov Decision Processes Pedro D’Argenio, Henrik Jensen, Bertrand Jeannet, Kim Larsen x8x8 x=8 x5x5 x4x4 send success wait x:=0 x:=x+1 process A { var x : uint(4); t : uint(10); init #send and x=0 and t=0; loc send: when x>=4 goto { success 0.01 ; wait 0.99 }; when x<5 and t<200 goto send assign {x:=x+1; t:=t+1}; loc wait: when x=8 goto send assign {x:=0}; when x<8 and t<200 goto wait assign {x:=x+1; t:=t+1}; loc success: when true goto success; } system A; initial #A.send and A.x=0 and A.t=0; final #A.success and A.t<200; PAPM’01, PAPM’02

ARTIST2 NoE, Test & Verification Meeting 1 26 Partition/Refinement T

ARTIST2 NoE, Test & Verification Meeting 1 27 Partition/Refinement Theorem TTT