Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0 The Microarchitecture Level.

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Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The Microarchitecture Level Chapter 4

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The Data Path (1) The data path of the example microarchitecture used in this chapter.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Data path registers PC and MBR are byte registers N and Z are bit registers MAR – Memory Address Register MDR – Memory Data Register PC – Program Counter MBR – Memory Byte Register SP – Stack pointer LV – Local Variables CPP – Constant Pool Pointer TOS – Top of Stack OPC – utility register H – Holding register

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The Data Path (2) Useful combinations of ALU signals and the function performed.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Data Path Timing Timing diagram of one data path cycle.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Clocks Only actual clock is C1 The use of delays effectively define C2, C3, etc.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Memory Operation Mapping of the bits in MAR to the address bus.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Microinstructions The microinstruction format for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Microinstruction notes Next instruction refers to address in control store JMPC – set is unconditional jump (MBR or NEXT -> MPC) JAMN – set is jump if N is set ( or 0x100) JAMZ – set if jump if Z is set ( or 0x100) SLL8 – shift left 8 SRA1 – shift right 1 F0, F1, ENA, ENB, INVA, INC – ALU control lines Write – write memory (32 bit) Read – read memory (32 bit) Fetch – get byte of memory

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Microinstruction Control: The Mic-1 (1) The complete block diagram of our example microarchitecture, the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved MIC-1 notes MPC – Microcode program counter MIR – MicroInstruction Register The microcode contains the instructions that translate the instruction set into operations that control the data path. One view is that the microcode is an interperter that runs the Instruction Set code. The other view is that the microcode is a set of subroutines that are called by the instructions at the instruction set Architecture level.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Microinstruction Control: The Mic-1 (2) A microinstruction with JAMZ set to 1 has two potential successors.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Stacks (1) Use of a stack for storing local variables. (a) While A is active. (b) After A calls B. (c) After B calls C. (d) After C and B return and A calls D.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Stacks (2) Use of an operand stack for doing an arithmetic computation.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The IJVM Memory Model The various parts of the IJVM memory.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Memory Notes a)Constant Pool – read only b)Local Variable Frame c)Operand Stack ( compiler guarantees that it will not exceed limits) (SP points to top of this stack) d)Method Area Treated as a byte array (Holds program)

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The IJVM Instruction Set (1) The IJVM instruction set. The operands byte, const, and varnum are 1 byte. The operands disp, index, and offset are 2 bytes.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The IJVM Instruction Set (2) (a) Memory before executing INVOKEVIRTUAL. (b) After executing it.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The IJVM Instruction Set (3) (a) Memory before executing IRETURN. (b) After executing it.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Compiling Java to IJVM (1) (a) A Java fragment. (b) The corresponding Java assembly language. (c) The IJVM program in hexadecimal.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Compiling Java to IJVM (1) The stack after each instruction of Fig. 4-14(b).

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Microinstructions and Notation All permitted operations. Any of the above operations may be extended by adding ‘‘<< 8’’ to them to shift the result left by 1 byte. For example, a common operation is H = MBR << 8.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (1) The microprogram for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (2) The microprogram for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (3) The microprogram for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (4) The microprogram for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (5) The microprogram for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (6) The BIPUSH instruction format. (a) ILOAD with a 1-byte index. (b) WIDE ILOAD with a 2-byte index.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (7) The initial microinstruction sequence for ILOAD and WIDE ILOAD. The addresses are examples.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (8) The IINC instruction has two different operand fields.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Implementation of IJVM Using the Mic-1 (9) The situation at the start of various microinstructions. (a) Main1. (b) goto1. (c) goto2. (d) goto3. (e) goto4.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Merging the Interpreter Loop with the Microcode (1) Original microprogram sequence for executing POP.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Merging the Interpreter Loop with the Microcode (2) Enhanced microprogram sequence for executing POP.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved A Three Bus Architecture (1) Mic-1 code for executing ILOAD.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved A Three Bus Architecture (2) Three-bus code for executing ILOAD.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved A Three Bus Architecture (3) A fetch unit for the Mic-1.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved A Three Bus Architecture (4) A finite state machine for implementing the IFU.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Out-of-Order Execution and Register Renaming (1) A superscalar CPU with in-order issue and in-order completion.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Out-of-Order Execution and Register Renaming (2) A superscalar CPU with in-order issue and in-order completion.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Out-of-Order Execution and Register Renaming (3) Operation of a superscalar CPU with out-of-order issue and out of-order completion.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Speculative Execution (a) A program fragment. (b) The corresponding basic block graph.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Overview of the NetBurst Microarchitecture The block diagram of the Pentium 4.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The NetBurst Pipeline A simplified view of the Pentium 4 data path.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved Overview of the UltraSPARC III Cu Microarchitecture The block diagram of the UltraSPARC III Cu.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved UltraSPARC III Cu Pipeline A simplified representation of the UltraSPARC III Cu pipeline.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved The Microarchitecture of the 8051 CPU The microarchitecture of the 8051.