Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage VII: March 1 st 2004 COMPONENT LAYOUT Presentation #7: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip Integrated Circuit Design Project

Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Layout  Component Layout  Simulations  To be Done  Top Level Routing  Optimizations  Everything else… Integrated Circuit Design Project

Design Decisions & Problems DECISIONS Split ROM Added logic because of split rom Split into 4 sub-ROMs PROBLEMS Timing problems Routing Problems – Global Level Sizing of DFF to get equal rise and fall times Integrated Circuit Design Project

Implementing Rijndael Encryption on Chip with this in mind: – Throughput – Speed At least 350 Mhz –Size As dense as possible while maintaining a ratio of 1:1 Project Goals & Objectives Integrated Circuit Design Project

On-Chip Encryption to be used in: – Web servers High through put for passing through information Hardware encryption generally x faster than software Security of a private key greater if stored in hardware –Software keys can be hacked, stolen and used elsewhere Project Goals & Objectives Integrated Circuit Design Project

TOPLEVELSCHEMATICTOPLEVELSCHEMATIC

Updated Floorplan 325 um x 330 um Metal 3 Metal 2 Metal 1 Metal 4 SBOX and Control Logic Text DFFs and Add Round Key 5 th Round Key Expand Input to SBOX Logic & Select Output and Input Logic 4 Rounds of Key Expand 4 Rounds of Round Permutation Input/Output Logic CLK Divider Select & Input Logic SBOX and Control Logic Final Text Out Key DFFs and Input Logic

METAL 1

METAL 2

METAL 3

METAL 4

POLY

LAYOUT – NO METAL

LAYOUT – Buses

Clock Divider

Add Round Key

DFF Input

S-box Mux Tree In

Demux 20

S-box Mux Tree Out

Final Text Output

Round Permutation & DFF

Key Expand & DFF

S-box Mux Tree Out

DFF Input Key

Demux 10

S-BOX - ROM

D-FLIP FLOP LAYOUT Integrated Circuit Design Project

Waves D-FlipFlop Fall Time Integrated Circuit Design Project ps p

Waves D-FlipFlop Rise Time Integrated Circuit Design Project ns p

Waves D-FlipFlop Propagation Time Integrated Circuit Design Project ns p

DFF Setup Time Integrated Circuit Design Project ps p p

ROM Propogation Time p

Critical Path Integrated Circuit Design Project ps 1.03n

More on Critical Path Must include the setup time for DFF Actual Critical Path is about 1.2n Must double it as this logic only occurs on negative edge of clock Speed Estimation: 417MHz

Questions? Integrated Circuit Design Project