S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 18: Scaling Theory Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’08 Moore’s Law Moore’s Law. The number of transistors in an integrated circuit doubles every 2 years. IBM Cell 234M transistors in die size of 221 mm 2

S. Reda EN160 SP’08 Scaling of MOS transistors minimum feature size (gate length) 1.2nm Current oxide thickness ~ 1.0 – 2.0nm thickness  3 – 4 atomic layers of oxide Power supply voltage scaling

S. Reda EN160 SP’08 Scaling Avg transistor price is 0.1 μcent! Fewer and fewer companies can afford to have their own foundries Scaling of lithographic wavelength Number of transistors shipped

S. Reda EN160 SP’08 Device scaling (very idealistic NMOS transistor) doping increased by a factor of S scale Increasing the channel doping density decreases the depletion width  improves isolation between source and drain during OFF status  permits distance between the source and drain regions to be scaled (scaled down by L)

S. Reda EN160 SP’08 Implications of ideal device scaling

S. Reda EN160 SP’08 Historically frequency scaled by more than S Intel VP Patrick Gelsinger (ISSCC 2001) “If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun.”

S. Reda EN160 SP’08 Scaling of standby (leakage) power  Even if V t is kept constant after scaling, P off scales up by S if t ox is scaled down by S  V t must be scaled down if V DD is scaled down (otherwise I SAT is weaker and transistor is slow)  Standby power would further increase by 10  for every 0.1V reduction of V t Standby power bottleneck

S. Reda EN160 SP’08 Power/performance tradeoffs Threshold voltage (V t ) Power supply voltage (V dd ) increasing performance higher active power higher leakage [Taur, 01]

S. Reda EN160 SP’08 Interconnect scaling w: width of interconnect (layer dependant) s: spacing between interconnects with same layer h: dielectric thickness (spacing between interconnects in two vertically adjacent layers) l: length of interconnect t: thickness of interconnect

S. Reda EN160 SP’08 Constant thickness scaling versus reduced thickness scaling reduced thickness scaling constant thickness scaling

S. Reda EN160 SP’08 Implications of ideal interconnect scaling

S. Reda EN160 SP’08 Interconnect delay is dominating gate delay bottleneck Repeaters can help but…

S. Reda EN160 SP’08 With scaling the reachable radius of a buffer decreases  we need more and more buffers  A corner-to-corner (BL-UR) wire in Itanium (180nm) requires 6 repeaters to span die  Repeaters consume chip area; consume power; add vias repeaters required to buffer Itanium global interconnects bottleneck

S. Reda EN160 SP’08 Summary Done with chapter 4: Delay estimation Power estimation Interconnects and wire engineering Design Margins Scaling theory