Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction based on STG Unfoldings V. Khomenko, A. Madalinski and A. Yakovlev University of Newcastle upon Tyne

2 Signal Transition Graph (STG) Device VME Bus Controller lds ldtack d Data Transceiver Bus dsr dsw dtack dtack- dsr+ lds+ d- lds-ldtack- ldtack+ d+ dtack+ dsr-

3 Encoding conflicts pairs of semantically different states with the same binary encoding not distinguishable at the circuit level encoding conflicts have to be resolved before we can proceed with synthesis Transformations: signal insertion: introduces additional internal signal (‘memory’) helping to trace the current state concurrency reduction: introduces additional ordering constraints making some of the conflicting states unreachable  both are needed to explore a larger design space!

4 dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d M’’M’ dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d Example: CSC conflict

5 M’’M’ CSC resolution: signal insertion dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d csc+ csc

6 M’’M’ dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d CSC resolution: concurrency reduction dtack-dsr+ lds

7 Framework for visualisation & interactive resolution of encoding conflicts manual vs. automatic resolution of coding conflicts automatic  can produce sub-optimal solutions manual  crucial for finding good (low-latency, compact & elegant) synthesis solutions interactivity is good! visualisation concepts: emphasise essential information avoid information overload

8 STG unfolding partial order model infinite acyclic net, simple structure finite complete prefix finite initial part of unfolding contains all the reachable states alleviates state space explosion problem more visual then state graphs proven efficient for model checking

9 core State Graphs vs. Unfoldings lds- e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 12 e 10 e8e8 dsr+ ldtack+ dsr- ldtack- lds+ d+ dtack+ d- dtack- dsr+ lds+ M’ M’’ M’ M’’ dtack-dsr+ dtack-dsr+ dtack- dsr ldtack lds lds+ ldtack+ d+ dtack+ dsr- d

10 Visualisation of conflicts: Height map Core 1 Core 2 cores often overlap high-density areas are good candidates for signal insertion analogy with topographic maps A1 A2 A3 Core 3

11 Highest peak Height map: an example Core mapHeight map csc+

12 Resolution of encoding conflicts Core t+ t- Signal insertion: insert t+ in a core t- must be added outside the core preserving consistency inserted transitions must not trigger an input signal

13 Concurrency reduction addition of causal constraint, i.e. a new place u1u1 t (non-input) u2u2 Add a token if needed

14 Resolution of encoding conflicts Forward concurrency reduction: bringing forward the ending point of concurrency ‘dragging’ f into the core

15 Resolution of encoding conflicts Backward concurrency reduction: delaying starting point of concurrency ‘dragging’ f into the core

16 Resolution of encoding conflicts Concurrency reduction: an example p’ inputs: b,c,f; outputs: a,d,einputs: a,b; outputs: c,d,e forward backward

17 Overview of the resolution process concurrency reduction signal insertion phase 1 phase 2

18 Cost function cost = α 1 ·  + α 2 ·  logic – α 3 ·  core  : estimated delay caused by transformation  logic: estimated increase in complexity of logic  core: number of eliminated cores, α i : parameters chosen by the designer Calculated on the original unfolding prefix

19 Validity signal insertion: well-developed, e.g. weak bisimulation concurrency reduction: more challenging, e.g.: not even language-equivalent events can become dead introduction/disappearance of deadlocks

20 Validity aspects I/O interface preservation the interface between circuit and its environment should be preserved conformation no “wrong” behaviour should be introduced liveness no “interesting” behaviour should be completely eliminated technical restrictions boundedness, speed-independence, etc.

21 Validity notion natural to use partial order framework when speaking about concurrency reduction! plan: define a “valid realisation” relation on partial order analog of traces (processes) define “valid realisation” relation on systems

22 Validity notion: processes can easily eliminate silent actions (e.g. internal signals) preserving causality – abstraction ab c d  ab c d

23 Validity notion: processes step 1: increasing concurrency of inputs step 2: decreasing concurrency of outputs

24 step 1: increasing concurrency of inputs Validity notion: processes step 2: decreasing concurrency of outputs i1i1 i2i2 o i1i1 i2i2 o o1o1 o2o2 i o1o1 o2o2 i

25 Validity notion: processes i1i1 i2i2 o i1i1 i2i2 o o1o1 o2o2 i o1o1 o2o2 i i1i1 i2i2 o o1o1 o2o2 i i1i1 i2i2 o1o1 o2o2 i1i1 i2i2 o1o1 o2o2 i1i1 i2i2 o1o1 o2o2

26 Validity notion: systems valid realisation: e E E’ (transformed) (original) E e’ E’ (transformed) (original)

27 Validity notion: systems i2i2 i1i1 i1i1 i2i2 i2i2 i1i1 o2o2 o1o1 o1o1 o2o2 o2o2 o1o1 o o o o … … o o

28 Case study: AD converter controller signal insertion #phase 1phase 2cost 6|| Laf+ to Lr-->ready- 7Laf+ ->->ready-0 8->Ar-->ready-0 9-> Lr-->ready-1 10Laf+ ->start- ->1 11Laf+ ->|| ready+ to ready-1 concurrency reduction #causal constraintcost Core map

29 Conclusions combined framework for resolution of encoding conflicts based on cores in the STG unfolding larger design space – exploit the area/delay trade-off novel validity condition Future work more automation improving cost function performing transformation directly on the unfolding prefix rather than the STG