Team M1 Enigma Machine Adithya Attawar (M1-1) Shilpi Chakrabarti (M1-2) Zaven Gabriel (M1-3) Michael Sokolsky (M1-4) Design Manager: Prateek Goenka Week 6

Status Finished Finished –Behavioral Verilog and C simulation –Structural Verilog –SPICE Delay Diagrams –Optimization of logic and modules In Progress In Progress –Schematic Verification –Power Estimation –Floorplan –New Module Implementation To do To do –Layout –Testing –Simulation

Schematic Verification Most module schematics finished, tested individually Most module schematics finished, tested individually –Small modules (muxes, FFs) working –RAM & ROM Decoder module working Global routing, testing remains Global routing, testing remains –FSM, higher-level assembly/testing of modules within top-level design –Loadable wheel counters still have bugs

FSM Schematic

Memory Decoder

“decodesub” Module

8x5-bit Registers with Serial Input

Next Steps Power estimation Power estimation Refine the adder to improve rise/fall times (from Week 5) Refine the adder to improve rise/fall times (from Week 5) Find and fix bugs in loadable-counter module Find and fix bugs in loadable-counter module Make progress on implementing the new asymmetric-encryption module Make progress on implementing the new asymmetric-encryption module Verify schematic of entire design Verify schematic of entire design

Questions?