234262 Tutorial #6 Controller + DataPath part II 234262 – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.

Slides:



Advertisements
Similar presentations
– © Yohai Devir 2007 Technion - IIT Tutorial #10 MIPS commands.
Advertisements

CS 140 Lecture 10 Sequential Networks: Implementation Professor CK Cheng CSE Dept. UC San Diego 1.
Circuits require memory to store intermediate data
Register Cell Design.
CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits.
שאלת חזרה בקר ומסלול נתונים – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.
Tutorial #10 MIPS commands – © Yohai Devir 2007 Technion - IIT.
CS 151 Digital Systems Design Lecture 15 Magnitude Comparators and Multiplexers.
Tutorial #13 Solving MIPS Exam Problems 20: © Dima Elenbogen 2010, Technion 1.
שערים לוגיים – © Dima Elenbogen Wired AND – © Dima Elenbogen 2009.
Tutorial #7 Preventing combinatorial loops – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.
משטר דינמי – © Dima Elenbogen :00. הגדרת cd ו -pd cd - הזמן שעובר בין הרגע שראשון אותות הכניסה יוצא מתחום לוגי עד אשר אות המוצא יוצא מתחום.
שערים לוגיים – © Dima Elenbogen Wired AND – © Dima Elenbogen 2009.
Give qualifications of instructors: DAP
Tutorial #7 Preventing combinatorial loops – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.
שערים לוגיים – © Dima Elenbogen Wired AND – © Dima Elenbogen 2009.
Tutorial #13 Solving MIPS Exam Problems 01: © Dima Elenbogen 2010, Technion 1.
– © Yohai Devir 2007 Technion - IIT Tutorial #6 Controller + DataPath part II.
CS 140L Lecture 7 Professor CK Cheng 11/12/02. Transformation between Mealy and Moore Machines Algorithm: 1) For each NS, z = S i, j create a state S.
Tutorials #4-#5 Controller + DataPath design – © Yohai Devir 2007 Technion - IIT.
CS 140 Lecture 11 Professor CK Cheng 5/31/02. C1C2 CLK x(t) y(t) Sequential Network Implementation Mealy & Moore machine State Table  Netlist s(t) D(t)
משטר דינמי – © Dima Elenbogen :14. הגדרת cd ו -pd cd - הזמן שעובר בין הרגע שראשון אותות הכניסה יוצא מתחום לוגי עד אשר אות המוצא יוצא מתחום.
– © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT Tutorial #7 Preventing combinatorial loops.
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)
Datapath and Control Andreas Klappenecker CPSC321 Computer Architecture.
שאלה 9 – בקר ומסלול - נתונים נתונה המערכת הבאה של בקר ומסלול נתונים. כל הקווים העבים בשרטוט ה DP הם ברוחב n. ה -ADDER מחבר מודולו n 2. COMPARE הוא רכיב.
CS 140L Lecture 7 Transformation between Mealy and Moore Machines Professor CK Cheng CSE Dept. UC San Diego.
CS 151 Digital Systems Design Lecture 31 Read Only Memory (ROM)
Tutorial #6 Controller + DataPath part II – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.
Tutorial #6 Controller + DataPath part II – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.
9/15/09 - L25 Registers & Load Enable Copyright Joanne DeGroat, ECE, OSU1 Registers & Load Enable.
IKI Register-transfer Design
IAY 0600 Digitaalsüsteemide disain Register Transfer Level Design (GCD example) Lab. 7 Alexander Sudnitson Tallinn University of Technology.
DLD Lecture 26 Finite State Machine Design Procedure.
1 A counter counts Number of elements in counter determines how many different states we need For example, an eight-state counter can count eight steps.
CBP 2006Comp 4070 Concepts and Philosophy of Computing 1 Wrestling with Complex Stuff. With the Correct Approach, even the smallest guy will succeed!
Lab 7 : Overview State Machine : Moore Model Concept in designing a Vending Machine.
Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Basics of register-transfer design: –data paths and controllers; –ASM.
IAY 0600 Digital Systems Design Register Transfer Level Design (GCD example) Lab. 7 Alexander Sudnitson Tallinn University of Technology.
1  1998 Morgan Kaufmann Publishers Simple Implementation Include the functional units we need for each instruction Why do we need this stuff?
Computer Organization CS345 David Monismith Based upon notes by Dr. Bill Siever and notes from the Patterson and Hennessy Text.
System-on-Chip Design Analysis of Control Data Flow
Dr. ClincyLecture Slide 1 CS Chapter 3 (3A and ) Part 8 of 8 Dr. Clincy Professor of CS.
May 22, 2000Systems Architecture I1 Systems Architecture I (CS ) Lecture 14: A Simple Implementation of MIPS * Jeremy R. Johnson Mon. May 17, 2000.
George Mason University Finite State Machines Refresher ECE 545 Lecture 11.
Design a MIPS Processor (II)
Finite State Machines Mealy machine inputs Outputs next state function
Section 6: Asynchronous Circuits
IAY 0600 Digital Systems Design
Carry Look Ahead (CLA).
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
IAY 0600 Digital Systems Design
Simple Processor Control Unit
Solving MIPS Exam Problems
Lecture 3 CPU - Data Path for Branches
ECE 368: CAD-Based Logic Design Lecture Notes # 5
Tutorial #10 MIPS commands
תרגול 6 בקר ומסלול נתונים חלק שני
One-Hot Seq. Circuit Delay
תרגול 6 בקר ומסלול נתונים חלק שני
Systems Architecture I
IAS 0600 Digital Systems Design
Simple Implementation
Controllers and Datapaths
Lecture 17 State Machine Design Using SM Chart
Mealy and Moore Machines
Tutorials #4-#5 Coltroller + dataPath design
CS161 – Design and Architecture of Computer Systems
Arithmatic Logic Unit (ALU). ALU Input Data :  A0-A3  B0-B3 Output Data :  F0 – F3.
Presentation transcript:

Tutorial #6 Controller + DataPath part II – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

GCD (Euclid's algorithm) a is given at the first cycle and that b is given at the following cycle ALUOp CC AB – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

Other hardware – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

DP construction Variables… Operations… – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

DP flow chart (Moore) * – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

Switch implementation LdA AB ALUOp CC In SelB LdB SelA – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

AB ALUOp CC In SelB LdB SelA0101 Implementation – just as in tutorial 4… LdA – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

GCD – slower ALU AB ALUOp CC ALU In SelB LdB SelA – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

GCD – slower ALU – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

GCD – slower ALU – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

GCD – slower ALU ? – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

*

* GCD – slower ALU AB ALUOp CC ALU In SelB LdB SelA – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

GCD – slower ALU AB ALUOp CC ALU In SelB LdB SelA01 01 CC '0' ReadCC – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

AB ALUOp CC ALU In SelB LdB SelA – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

ALUop אות הסטטוס – © Dima Elenbogen 2009 Technion - IIT

ALUop אות הסטטוס – © Dima Elenbogen 2009 Technion - IIT

AB ALUOp CC ALU In SelB LdB SelA01 01 CC '0' ReadCC 1 0 ALU op Output comb. logics Transition comb. logics – © Dima Elenbogen 2009 Technion - IIT

ספחת סטטית FF של ALU OP חייב להיות חסר ספחת סטטית!  ספחת סטטית היא תופעה שבה יחידה יכולה לשנות את המוצא שלה כאשר הכניסות שלה לא השתנו – © Dima Elenbogen 2009 Technion - IIT

– © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

DP mealy (regular ALU) – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

Controller Mealy – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

– © Yohai Devir 2007 Technion - IIT Controller Mealy ?

selA=0 selB=0 if (CC==pos) ldA, OP=A-B if (CC==neg) ldB, OP=B-A CC=pos CC=neg ? – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

ALU OP depends on CC ALU ! AB ALUOp CC ALU In SelB LdB SelA01 01 Combinatorial Logics NS CS LdA – © Dima Elenbogen 2009 Technion - IIT

ALU OP depends on CC ALU ! AB ALUOp CC ALU In SelB LdB SelA01 01 Comb. Logics NS CS LdA – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

Mistake by standard notations – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT

Mealy Controller – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT