E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Wed. Sept 24 TEA encryption C & Behavioral Verilog Simulation Secure Electronic Voting Terminal

E-Voting Overall System Block Diagram Machine Initialization FSM User Identification FSM Selection FSM Confirmation FSM Card Reader Finger Print Scanner User Input Write-In SRAM (64 byte) ID SRAM (8 byte) Encryption Key SRAM (32 byte) Choice SRAM (4 byte) Discrete Buttons Keyboard DISPLAY 85 8 Central Computer 16 Encryption Decryption Transmit Receive Regis- ter 16 Serial Output Port choices of candidates per page 4 pages 1 write-in per page T: 320 T: 160 T: 240 T: 480 T: 192 T: 384 T: 3072 T: 1536 T: 5000 T: 240 T: 384 T: 5000

Tiny Encryption Algorithm Project Specs Original Implementation: 64-bit blocks: Two 32-bit inputs 128-bit key: Four 32-bit keys (K[0], K[1], K[2], K[3]) Feistel Structure: Symmetric structure used in block ciphers “Magic” constant: 9E3779B9 (Delta) = 2^32 / (golden ratio) 64 Feistel rounds = 32 cycles E-Voting Machine Implementation: 16-bit blocks: Two 8-bit inputs 32-bit key: Four 8-bit keys 32 Feistel rounds = 16 cycles Decision: Scale up 1.6 golden ratio by magnitude of 10 to 16, scale (2^16) by 10 = and do division / 16 to get Delta. Avoids using Floating point for key scheduler. New Delta = A000, truncate least sig bit to A000 to fit 16 bits when decrypting, since A00 * 8 cycles = 0x5000 Hardware: 4, 5-bit Shifters 16-bit Multipliers 16-bit Adder / Subtractor

Tiny Encryption Algorithm C Full Implementation #include void tea_encrypt(uint8_t* v, uint8_t* k) { uint8_t v0=v[0], v1=v[1]; uint8_t k0=k[0], k1=k[1], k2=k[2], k3=k[3]; uint16_t delta=0x0A00, sum; uint8_t n; sum=0; for (n=0; n < 8; n++) { sum += delta; v0 += ((v1 >5)+k1); v1 += ((v0 >5)+k3); printf("Iteration: 0x%x %x\n", v0, v1); printf("Sum: 0x%x\n", sum); } v[0]=v0; v[1]=v1; } void tea_decrypt(uint8_t* v, uint8_t* k) { uint8_t v0=v[0], v1=v[1]; uint8_t k0=k[0], k1=k[1], k2=k[2], k3=k[3]; uint8_t n; uint16_t delta=0x0A00, sum; sum=0x5000; for (n=0; n < 8; n++) { v1 -= ((v0 >5)+k3); v0 -= ((v1 >5)+k1); sum -= delta ; printf("Iteration: 0x%x %x\n", v0, v1); printf("Sum: 0x%x\n", sum); } v[0]=v0; v[1]=v1; } int main(int artgc, char **argv, char **env) { uint8_t v[2]; /* Plaintext */ uint8_t k[4]; /* Key */ /* Input to Plain Text */ v[0] = 0x12; v[1] = 0x34; printf("\nInput Data: "); printf(" v = 0x%x %x\n\n", v[0], v[1]); /* Key */ k[0] = 0x77; k[1] = 0x8c; k[2] = 0xae; k[3] = 0x38; printf("Key = 0x%x %x %x %x\n\n", k[0], k[1], k[2], k[3]); /* Now call Encode Routine */ tea_encrypt(v, k); printf("Encoded data = 0x%x %x\n\n", v[0], v[1]); /* Now call Decode Routine */ tea_decrypt(v, k); printf("Decoded data = 0x%x %x\n", v[0], v[1]); return(0); }

Tiny Encryption Algorithm C Simulation Results Input Data: v = 0x12 34 Key = 0x77 8c ae 38 Iteration: 0x20 eb Sum: 0xa00 Iteration: 0x7f c5 Sum: 0x1400 Iteration: 0xf 6e Sum: 0x1e00 Iteration: 0xc5 73 Sum: 0x2800 Iteration: 0x20 2a Sum: 0x3200 Iteration: 0xd0 6a Sum: 0x3c00 Iteration: 0xc2 9c Sum: 0x4600 Iteration: 0xfd 58 Sum: 0x5000 Encoded data = 0xfd 58 Iteration: 0xc2 9c Sum: 0x4600 Iteration: 0xd0 6a Sum: 0x3c00 Iteration: 0x20 2a Sum: 0x3200 Iteration: 0xc5 73 Sum: 0x2800 Iteration: 0xf 6e Sum: 0x1e00 Iteration: 0x7f c5 Sum: 0x1400 Iteration: 0x20 eb Sum: 0xa00 Iteration: 0x12 34 Sum: 0x0 Decoded data = 0x12 34

Tiny Encryption Algorithm Verilog Implementation module CommsBlock(V0_temp, V0, V1, sum, transmit_sig, decrypt_out, arr_V, arr_K, receive_sig, encrypt_in, clk); output [7:0] V0, V1, V0_temp; output [15:0] sum; output transmit_sig; output decrypt_out; input [15:0] arr_V; input [31:0] arr_K; input receive_sig; // If registered value = 1, enable decryption of msg input encrypt_in; // If registered value = 1, enable encryption of msg input clk; reg [7:0] V0, V1, V0_temp; reg [7:0] K0, K1, K2, K3; reg [15:0] sum; reg encrypt_reg, decrypt_reg; reg decrypt_out, transmit_sig, transmit_reg, receive_reg; (posedge clk) begin encrypt_reg <= encrypt_in; decrypt_out <= decrypt_reg; transmit_sig <= transmit_reg; receive_reg <= receive_sig; end integer i; (encrypt_reg) begin K3[7:0] <= arr_K[7:0]; K2[7:0] <= arr_K[15:8]; K1[7:0] <= arr_K[23:16]; K0[7:0] <= arr_K[31:24]; V1[7:0] <= arr_V[7:0]; V0[7:0] <= arr_V[15:8]; sum[15:0] = 0; for(i=0; i < 8; i = i + 1) begin sum[15:0] = sum[15:0] + 16'h0A00; #5 V0 = V0 + ((V1 >> 5) + K1); #10 V1 = V1 + ((V0 >> 5) + K3); end transmit_reg = 1; //Assert Transmit signal, wait for Receive signal (user input) end integer j; (receive_reg) begin sum = 16'h5000; for(j=0; j < 8; j = j + 1) begin V1 = V1 - ((V0 >> 5) + K3); V0 = V0 - ((V1 >> 5) + K1); sum[15:0] = sum[15:0] - 16'h0A00; end decrypt_reg = 1; //Assert Decrypt as finished end endmodule module test_CommsBlock; //Testbench for Tiny Encryption Algorithm and Comms block wire [7:0] V0, V1, V0_temp; wire [15:0] sum; wire transmit_sig_wire; wire decrypt_out_wire; reg [15:0] arr_V_reg; reg [31:0] arr_K_reg; reg encrypt_in_reg; reg receive_sig_reg; reg clk; CommsBlock myCommsBlock(V0_temp, V0, V1, sum, transmit_sig_wire, decrypt_out_wire, arr_V_reg, arr_K_reg, receive_sig_reg, encrypt_in_reg, clk); always #20 clk = ~clk; initial begin $monitor($time, " V0_temp=%h, V0=%h, V1=%h, sum=%h, tranmit_sig=%h, decrypt_out=%h, arr_V=%h, arr_K=%h, receive_sig=%h, encrypt_in_reg=%h, clk=%h", V0_temp, V0, V1, sum, transmit_sig_wire, decrypt_out_wire, arr_V_reg, arr_K_reg, receive_sig_reg, encrypt_in_reg, clk); clk = 0; arr_V_reg = 16'h0; arr_K_reg = 32'h0; encrypt_in_reg = 0; receive_sig_reg = 0; #3 arr_V_reg = 16'h1234; arr_K_reg = 32'h778cae38; encrypt_in_reg = 1; receive_sig_reg = 0; #200 $stop; end endmodule

Questions? Thank you!