Physical States for Bits
Black Box Representations
Truth Tables
Basic Logic Gates
NAND and NOR gates
Sum of Products Circuits
Timing Diagrams
Logic Levels for CMOS
The concept of voltage- controlled resistance
nMOS transistor
pMOS transistor
Now we put together nMOS and pMOS transistors to create an inverter
Switch Model for CMOS inverter
Logical operation of CMOS inverter
Explanation of 2-input CMOS NAND gate
Switch Model for NAND realized in CMOS
Explanation of CMOS NOR
CMOS NAND with 3 inputs
Example of realization of large NAND gates in CMOS
Buffers realized in CMOS
AND gate in CMOS
AND-OR-INVERT gate in CMOS
CMOS OR-AND-INVERT
Data Sheets and how to use them
Test Circuits and Waveforms
Input-Output Characteristics
Logic Levels and Noise Margins for CMOS logic family
Resistive Models of Inverters
Resistive model for CMOS LOW output with resistive load
Black Box Representations Resistive model for CMOS HIGH output with resistive load
Circuit defintions to calculate currents
Output loading specifications
Estimating sink and source currents
CMOS inverters with nonideal input voltages
Black Box Representations CMOS inverter with load and nonideal 1.5 voltage input
Black Box Representations CMOS inverter with load and nonideal 3.5 voltage input
What to do with non-used inputs?
Transition times
How to analyze transition times for CMOS output?
Model of HIGH-to-LOW transition
Black Box Representations