CaV 2003 CbCb 1 Concurrency and Verification What? Why? How?

CaV 2003 CbCb 2 What? Validation and Verification of software and hardware DESIGNS! (E.g., real time systems, embedded systems, communication protocols)

CaV 2003 CbCb 3 A REAL real time system

CaV 2003 CbCb 4 Embedded Systems SyncMaster 17GLsi Telephone Tamagotchi Mobile Phone Digital Watch

CaV 2003 CbCb 5 Why? zTesting/simulation of designs/implementations may not reveal error zFormal verification (=exhaustive testing) of design provides 100% coverage zTOOL support.

CaV 2003 CbCb 6 Tools Logic Temporal Logic Modal Logic MSOL Algorithmic (Timed) Automata Theory Graph Theory BDDs Polyhedra Manipulation Semantics Concurrency Theory Abstract Interpretation Compositionality Models for real-time & hybrid systems HOL TLP Applications PVS ALF SPIN MONAUPPAAL

CaV 2003 CbCb 7 Model Checking TOOL System Description A Requirement F Yes, Prototypes Executable Code Test sequences No! Debugging Information Tools: UPPAAL, CPN, SPIN, VisualSTATE, Statemate, Verilog, Formalcheck,...

CaV 2003 CbCb 8 System Description Unified Model = State Machine! a b x y a? b? x! y!b? Control states Input ports Output ports

CaV 2003 CbCb 9 Train Simulator 1421 machines transitions 2981 inputs 2667 outputs 3204 local states Declare state sp.: 10^476 BUGS ? VVS visualSTATE

CaV 2003 CbCb 10 ‘State Explosion’ problem a cb ,a 4,a 3,a4,a 1,b2,b 3,b4,b 1,c2,c 3,c4,c All combinations = exponential in no. of components M1 M2 M1 x M2

CaV 2003 CbCb 11 Intelligent Light Control OffLightBright press? WANT: if press is issued twice quickly then the light will get brighter; otherwise the light is turned off.

CaV 2003 CbCb 12 Intelligent Light Control OffLightBright press? Solution: Add real-valued clock x X:=0 X<=3 X>3

CaV 2003 CbCb 13 Timed Automata n m a Alur & Dill 1990 Clocks: x, y x 3 x := 0 Guard Boolean combination of comp with integer bounds Reset Action perfomed on clocks Transitions ( n, x=2.4, y= ) ( n, x=3.5, y= ) e(1.1) ( n, x=2.4, y= ) ( m, x=0, y= ) a State ( location, x=v, y=u ) where v,u are in R Action used for synchronization

CaV 2003 CbCb 14 Model Checking TOOL System Description A Requirement F Yes, Prototypes Executable Code Test sequences No! Debugging Information Tools: UPPAAL, CPN, SPIN, VisualSTATE, Statemate, Verilog, Formalcheck,...

CaV 2003 CbCb 15 Computation Tree Logic, CTL Clarke & Emerson 1980 Syntax

CaV 2003 CbCb 16 TCTL = CTL + Time E[  U  ], A[  U  ] - like in CTL No EX 

CaV 2003 CbCb 17 Infinite State Space?

CaV 2003 CbCb 18 Regions Alur & Dill: A Theory of Timed Automata, TCS 126, , 1994 Berthomieu & Menasche: An Enumerative Approach for Analyzing Timed Petri Nets, Information Processing 83, 1983 Berthomieu & Diaz: Modelling and Verification of Time Dependent Systems Using Time Petri Nets, IEEE Trans. on Soft. Eng. 17 (3), 1991

CaV 2003 CbCb 19 Roughly speaking.... Model checking a timed automata against a TCTL-formula amounts to model checking its region graph against a CTL-formula Model checking a timed automata against a TCTL-formula amounts to model checking its region graph against a CTL-formula

CaV 2003 CbCb 20 Complexity However S sys may be EXPONENTIAL in number of parallel components! -- FIXPOINT COMPUTATIONS may be carried out using ROBDD’s (Reduced Ordered Binary Decision Diagrams) Bryant, 86 However S sys may be EXPONENTIAL in number of parallel components! -- FIXPOINT COMPUTATIONS may be carried out using ROBDD’s (Reduced Ordered Binary Decision Diagrams) Bryant, 86

CaV 2003 CbCb 21 Problem to be solved   Model Checking TCTL is PSPACE-hard

CaV 2003 CbCb 22 Research opportunities zIndustrial Applications zApplications to Communication Protocols zApplication Area for Algorithmics zConcrete Projects: yVerification -> Testing ySpecifications with local modalities

CaV 2003 CbCb 23 Course material zJoost-Pieter Katoen: zConcepts, Algorithms, and Tools

CaV 2003 CbCb 24 Course structure zStudent presentations: zBrief overview of main contents zCritical assessment zExamples, applications zFollow-up on literature zSelection and solutions to exercises

CaV 2003 CbCb 25 Student presentations z1. Linear temporal logic, PLTL (47--66) z2. PLTL model checking ( ) z3. Computation tree logic, CTL ( ) z4. Real-time CTL, TCTL ( ) z5. State-space reduction ( )