EECE 344 – Microprocessors Quick Review

Information Representation Integer representation – whole numbers –Unsigned binary –2’s complement –Excess codes Floating point representation – IEEE 32 bit normalized numbers Other: instruction, address, parity, etc.

Basic Computer Architecture Fundamental principle: fetch-decode-execute cycle Instruction types –Work: logic, arithmetic –Movement: between registers, to/from memory –Program control: behavior of program –System control: behavior of system

Comp Arch Information (1) “Normal” registers: MAR, IR, PC, Status, General purpose registers Registers: hold values for work, movement activities as determined by program Memory – used to store programs and data Address space: for both memory and devices. 2 ADR locations for ADR bits

Comp Arch Information (2) Memory Mapped I/O  elements can be addressed like memory locations –I/O devices controlled by writing bits to registers located at specific memory addresses –Status determined by reading memory locations –Data transfer to/from I/O devices done by instructions acting as if working with memory

Comp Arch Information (3) Register set: hold values for work, movement instructions Alternate register set: additional registers allow for fast, easy context switch Complex Instruction Set Computer (CISC) – complex addressing modes – operands located in memory – complexity of program in complex instructions

Comp Arch Information (4) Reduced Instruction Set Computer (RISC) –Strive for single cycle execution –Work done only in registers –Simple addressing modes –Complexity in instruction groups, speed

Comp Arch Information (5) Control registers: used for system control –System status/control (PSR, GCR, GSR) –Interrupt activities (VBR, EPC, EPSR, FPC, FPSR) –Operating System functions (SS0 – SS4)

Interrupt System (1) Provide timely access to processor facilities Mechanism for returning to program without any program change Caused by events needing attention –Errors (div by 0, illegal instr, priv violation, etc) –Intentional events of system (bkpt, traps, etc) –External events (timers, UART, keypad, etc) Response activity contained in ISR

Interrupt System (2) Determine cause of interrupt, which ISR to invoke –Concept of vector for one of several ISRs –Concept of polling for multiple interrupts that share a single ISR –Use of LSB of ISR address to specify reg set –Interrupt controller identifies which interrupts are enabled (bits in NIER) and requesting service (bits in NIPND)

Interrupt System (3): Initialization Activities that occur only once, to allow participation in interrupt system or identify details of interrupt process –Creation of ISRs to deal with interrupt action –Setup of registers in individual functional units –Building Int Vector Table, setup of VBR –Set bits in Interrupt Controller (NIER, FIER) –Setup of PSR (IE, EE, FE)

Interrupt System (4): Steady State Activity defined by ISR (user supplied) In MMC2001, user interrupts: vector 10 –NIPND has info about which interrupt needs service –User must deal with possible events efficiently –User resets flags, re-establish setup condition Return from interrupt – return PC, PSR

MMC2001 Subsystems We have dealt with most MMC2001 subsystems –UART (2 channels) –PWM (6 channels) –Timer –Keypad –LCD –Interrupt controller

Techniques Used in EECE 344 Work accomplished by machine level instructions Subroutines to compartmentalize activity –Subroutine linkage –Parameter passing Movement of information using registers Movement of information using stack Mailbox technique for sending information