Tera-Pixel APS for CALICE Progress 19 th January 2007

Recent Activity IDR Foundry –Deep P implant –Submission date changed! Logic layouts well underway –Slightly larger than initial predictions Pixel layouts in early stages –Example Capacitor technology change

Area Estimates (from 6 th Sept 06) 26 bits ~ 100um 19 registers ~ 50um Mask + sample Mux Logic + Buffering SRAM controller Mask: 8.5um per 16 channels Local data buffers for global readout Mask + sample Select logic Bidir SR: 8.2um per 10 cells SRAM controller ~16.5u~25.5u 50  80um

Logic layouts: Actual sizes SRAM bank 126um Rd/Wr 22um Latch 21um Mux ~33um SR ~ (50 micron row pitch)

Likely Pixel Arrangement

Pixel Layout

Capacitor Technology MIM capNWcap NW N+ DPW P Substrate Top Metal Metal 1 Metal 300ns Final pulse 300ns