1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 10 MAD MAC th April, 2006 Top-Level Layout W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2 MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small modules Top level layouts, Extractions, LVS, Simulations -> To be done  Full Chip Layout (50% complete) and Simulation

3 RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Ovf Checker Leading 0 Anticipator Input Output 16 Reg Y Block Diagram

4 Design Decisions Optimized the multiplier by using a carry look-ahead adder instead of a regular ripple carry adder in the last stage. –Allowed us to remove one of the pipeline stages from the multiplier because the prop delay went down. Maximum of 8 Flip Flops per Pulse Generator

5 Timing Diagram Pipeline stage 1 Pipeline stage 2 Pipeline stage 3 Pipeline stage 4 Multiplier lower 7 outputs Multiplier top 15 outputs AdderNormalize Exponent calculator AlignZero Counter Round Holds exponent calculator Overflow Checker

6 Floorplan

7 Full Chip Layout Progress….

8 The Sad Story of Exponents

9 Exponents Schematic

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11 New Exponents Layout

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13 8-bit Register

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15 Round Layout

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17 Trans. Count Schematic Delay Layout Delay Multiplier nOptimizing… Exponents n1.2n Align500480p637p Adder n1.7n Leading p551p Normalize942407p437p Round462864p986p OvfCheck100453p475p Registers p193p Total

18 Area:um 2 Schematic Power: mW (350Mhz) Layout Power: mW Multiplier16, Optimizing… Exponents5, Align3, Adder13, Leading 01, Normalize3, Round1, OvfCheck Total 67,619--

19 Thoughts Setup Time issues with having back to back registers. Probably need to buffer in between?

20 Questions??