Built-In Test and Calibration of DAC/ADC Using A Low- Resolution Dithering DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn.

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Presentation transcript:

Built-In Test and Calibration of DAC/ADC Using A Low- Resolution Dithering DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University 17th IEEE North Atlantic Test Workshop

The 17 th IEEE North Atlantic Test Workshop’082 Outline Overview Test of DAC Polynomial fitting algorithm DAC calibration by dithering DAC Test and calibration of ADC Simulation results Summary

The 17 th IEEE North Atlantic Test Workshop’083 Overview Built-in test solution for mixed-signal system-on-chips (SoCs) Testing and characterizing non-linearity of on-chip DAC/ADCs Output calibration and error compensation for better linearity Low cost for design and manufacturing

The 17 th IEEE North Atlantic Test Workshop’084 Typical Mixed-signal SoC

The 17 th IEEE North Atlantic Test Workshop’085 Non-linearity Errors INL error

The 17 th IEEE North Atlantic Test Workshop’086 Proposed BIST Scheme Linear analog outputs Linear digital code outputs

The 17 th IEEE North Atlantic Test Workshop’087 Third-Order Polynomial Fitting Proposed by S.K. Sunter in ITC’96 Divide DAC transfer function into four sections Combine function outputs of each section (S0, S1, S2, S3) Calculate four coefficients (b0, b1, b2, b3) by easily- generated equations

The 17 th IEEE North Atlantic Test Workshop’088 Test of On-Chip DAC Fitting for INL error

The 17 th IEEE North Atlantic Test Workshop’089 Design of ΣΔ Modulator α SNR(dB) OSR LSB dB

The 17 th IEEE North Atlantic Test Workshop’0810 Simulation Results for On-Chip DAC On-chip DAC INL errorPolynomial fitting for INL error Fitting results through 6-bit dithering DACFinal analog outputs by calibrated DAC

The 17 th IEEE North Atlantic Test Workshop’0811 Test of On-Chip ADC Calibrated DAC to generate linear analog output INL error

The 17 th IEEE North Atlantic Test Workshop’0812 Summary A built-in test and calibration scheme for on-chip DAC/ADC is proposed A polynomial fitting algorithm is used to fix non- linearity error of DAC/ADC outputs Fault tolerance factor can be chosen for different applications Simulation results show that linearity is significantly improved after calibration Future research work:  Reduce the testing time  Improve the fitting algorithm for even higher linearity

THANKS Q&A