STG-based synthesis and Petrify J. Cortadella (Univ. Politècnica Catalunya) Mike Kishinevsky (Intel Corporation) Alex Kondratyev (University of Aizu) Luciano Lavagno (Universitá di Udine) Enric Pastor (Univ. Politècnica Catalunya) Alexander Taubin (University of Aizu) Alex Yakovlev (Univ. Newcastle upon Tyne)

What is it about? u This tutorial is about the synthesis of asynchronous circuits from behavioral specifications. u STGs can specify I/O concurrency (based on Petri nets). u STGs specify behavior at a level in which logic synthesis techniques can be applied. u Speed-independent and timed circuits can be derived.

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

Outline u Overview u Synthesis steps –Specification (STGs) –State encoding –Logic synthesis, decomposition and mapping u Synthesis with relative timing u Conclusions

x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z

x y z x+ x- y+ y- z+ z-

x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y x y+ z- 010 y-

xyz 000 x+ 100 y+ z+ y x y+ z- 010 y- Next-state functions

x z y

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK-DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

Circuit synthesis u Goal: –Derive a hazard-free circuit under a given delay model and mode of operation

Modes of operation Current state Next state u Fundamental mode –Single-input changes –Multiple-input changes u Input / Output mode –Concurrency circuit / environment

Speed independence u Delay model –Unbounded gate / environment delays –Certain wire delays shorter than certain paths in the circuit u Conditions for implementability: –Consistency –Complete State Coding –Output persistency

Other synthesis approaches u Burst-mode machines –Mealy-like FSMs –Fundamental mode (slow environment) u VLSI programming –Syntax-directed translation from CSP (“Communicating Sequential Processes”) –No logic synthesis –Circuit size ~ Size of the specification

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

State Graph (Read cycle) DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS (DSr, DTACK, LDTACK, LDS, D)

QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1 

Karnaugh map for LDS DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS = /1?

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

Concurrency reduction LDS- LDS+ LDS DSr+

Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

State encoding conflicts LDS- LDTACK- LDTACK+ LDS

Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

Complex-gate implementation

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

Hazards a b c x 0 abcx b a c

Hazards abcx b a c+ a b z c x

Decomposition u Global acknowledgement u Generating candidates u Hazard-free signal insertion –Event insertion –Signal insertion

Global acknowledgement a b c z a b d y d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

a b c z a b d y How about 2-input gates ? d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

a b c z a b d y How about 2-input gates ? d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

a b c z a b d y How about 2-input gates ? 0 0 d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

a b c z a b d y How about 2-input gates ? d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

c z d y How about 2-input gates ? a b d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

Strategy for logic decomposition u Each decomposition defines a new internal signal u Method: Insert new internal signals such that –After resynthesis, some large gates are decomposed –The new specification is hazard-free u Generation of candidates for decomposition: –Algebraic factorization –Boolean factorization (boolean relations)

y- z-w- y+x+ z+ x- w y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Decomposition example

yz=1 yz= y- y+ x- x+ w+ w- z+ z- w- z- y+ x y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ C C x y x y w z x y z y z w z w z y

s- s+ s- s=1 s= y+ x- w+ z+ z x+ w- z- y+ x y+ z C C x y x y w z x y z w z w z y s y-

s- s+ s- s=1 s= y+ x- w+ z+ z x+ w- z- y+ x y+ z y- z-w- y+x+ z+ x- w+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+

C C x y x y w z x y z y z w z w z y yz=1 yz= y- y+ x- x+ w+ w- z+ z- w- z- y+ x+

s- s+ s=1 s= x- w+ z x+ w- z- y+ x y+ z y- z-w- y+x+ z+ x- w+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ z- is delayed by the new transition s- !

yz=1 yz= y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ C C x y x y w z x y z w z w z yyyyyyy y- y+ x- x+ w+ w- z+ z- w- z- y+ x+

Signal insertion for function F State Graph F=0F=1 Insertion by input borders F- F+

Event insertion a b ER(x) c x x x x b SR(x) a

Properties to preserve a a b b a a b b a a b b x a a b b a a b b b a a b b x x a is persistent a is disabled by b = hazards

Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

Timing assumptions in design flow u Speed-independent: wire delays after a fork shorter than fan-out gate delays u Burst-mode: circuit stabilizes between two changes at the inputs u Timed circuits: Absolute bounds on gate / environment delays are known a priori (before physical design)

Relative Timing Circuits u Assumptions: “a before b” for concurrent and ordered events u Used by the tool to derive a circuit and timing constraints that must be met in physical design flow u Applied to design of the Rotating Asynchronous Pentium Processor(TM) Instruction Decoder (K.Stevens, S.Rotem et al. Intel Corporation)

Lazy Transition Systems ER (LDS+) EnR (LDS-) LDS- LDS+ LDS- DTACK- FR (LDS-) Event LDS- is lazy: firing = subset of enabling

Timing assumptions u (a before b) for concurrent events: concurrency reduction for firing and enabling u (a before b) f or ordered events: early enabling u (a simultaneous to b wrt c) for triples of events: combination of the above

Netlist with SI timing constraints LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK csc map

Adding timing assumptions (I) LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK csc map LDTACK- before DSr+ FAST SLOW

Adding timing assumptions (I) DTACK D DSr LDS LDTACK csc map LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDTACK- before DSr+

State space domain LDTACK- before DSr+ LDTACK- DSr+

State space domain LDTACK- before DSr+ LDTACK- DSr+

State space domain LDTACK- before DSr+ LDTACK- DSr+ Two more unreachable states

Boolean domain DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS = /1?

Boolean domain DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS = One more DC vector for all signalsOne state conflict is removed

Netlist with one constraint LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK csc map

Netlist with one constraint LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK LDTACK- before DSr+ TIMING CONSTRAINT

Timing assumptions u (a before b) for concurrent events: concurrency reduction for firing and enabling u (a before b) f or ordered events: early enabling u (a simultaneous to b wrt c) for triples of events: combination of the above

Ordered events: early enabling a c b a a c b a b b c c F G Logic for gate c may change

Adding timing assumptions (II) LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK D- before LDS-

State space domain LDS- D- Reachable space is unchanged For LDS- enabling can be changed in one state D- before LDS- Potential enabling for LDS- DSr-

Boolean domain DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS =

Boolean domain DTACK DSr D LDTACK DTACK DSr D LDTACK LDS = 0 LDS = One more DC vector for one signal: LDS If used: LDS = DSr, otherwise: LDS = DSr + D

Before early enabling LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ DTACK D DSr LDS LDTACK

Netlist with two constraints LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDTACK- before DSr+ and D- before LDS- TIMING CONSTRAINTS DTACK D DSr LDS LDTACK Both timing assumptions are used for optimization and become constraints

Backannotation u Timed circuits require post-verification u Can synthesis tools help ? –Report the least stringent set of timing assumptions required for the correctness of the circuit –Not all initial timing assumptions may be required u Petrify reports a set of firing order constraints that guarantee the circuit correctness

Experiments u Assumption: delays are controllable in physical design u 2-3x improvement in area/delay wrt to SI (K.Stevens, S.Rotem et al. Intel Corporation) –Rotating Asynchronous Pentium Processor(TM) –Instruction Decoder (Async’99)

Summary u Synthesis of asynchronous circuits can be automated at gate level (logic synthesis) u Timing assumptions/constraints are essential to compete with synchronous circuits u Relative timing seems to be a promising approach for specification and synthesis u High-level and logic synthesis can be combined (e.g. CSP  Petri net  circuit)

Petrify u The synthesis methodology presented in this tutorial is handled by petrify u but also... –Concurrency reduction –Automatic handshake expansion (2-4 phase) –Noise isolation –Synthesis with gC elements and gate libraries –Synthesis of Petri nets –Synthesis of Petri nets (crucial for backannotation) –...

Petrify: implementation details u 50,000 lines of code + SIS (data structures & logic synthesis) + BDD package (symbolic manipulation) + dot (graph visualization package from AT&T) u BDD-based implementation: –Reachability analysis –Manipulation of sets of states –Boolean minimization

Petrify References Tutorial for the designer Binaries (for several platforms)