E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Wed, Oct 29 Functional Layout Secure Electronic Voting Terminal

COMMS Full Schematic Components FF 8 bit (2) FF_C 16 bit (1) XOR 8 bit (4) Inv (1) FA 8bit (4) FA 16 bit (1) FA shift 4/5 bit (4) 8 bit 2:1 MUX(4) For all COMMs block Cell height:

New: Flip Flop with Clear Schematic

New: 1 bit Flip Flop with Clear Layout

1 bit Full Adder Layout Old New Preserves height. Bi-directional poly Eliminates metal 3 interconnect

8 bit Full Adder Layout

1 bit D Flip Flop Layout

8 bit D Flip Flop Layout

1 bit 2:1 MUX Layout Old New Preserves height. Eliminates metal 2 interconnect A lot easier for routing

8 bit D Flip Flop Layout

XOR Layout

FSM state register NOR + srFF + inverter M1 and M2 only 1.9 um/t Uses wrongway poly

FSM state registers

Tester Setup with each state driving the next proceed Min sized inverters drive the input Internal capacitance for loading Extracted simulation problems

State Register Testing

SRAM Write Simulation (1)

SRAM Write Simulation (2)

SRAM Read function Tester

SRAM Read Simulation (1)

SRAM Read Simulation (2)

SRAM Read Simulation (3)

SRAM layout

Decoder Layout in progress…

Questions? Thank you!