Analytical 2D Modeling of Sub-100 nm MOSFETs Using Conformal Mapping Techniques Benjamin Iñiguez Universitat Rovira i Virgili (URV), Tarragona, E-43001,

Slides:



Advertisements
Similar presentations
Lecture Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Introduction 1.
Advertisements

ECA1212 Introduction to Electrical & Electronics Engineering Chapter 6: Field Effect Transistor by Muhazam Mustapha, October 2011.
R. van Langevelde, A.J. Scholten Philips Research, The Netherlands
EE130/230A Discussion 12 Peng Zheng 1. Velocity Saturation Velocity saturation limits I Dsat in sub-micron MOSFETS Simple model: E sat is the electric.
Metal Oxide Semiconductor Field Effect Transistors
COMPACT MODEL FOR LONG-CHANNEL SYMMETRIC DOPED DG COMPACT MODEL FOR LONG-CHANNEL SYMMETRIC DOPED DG Antonio Cerdeira 1, Oana Moldovan 2, Benjamín Iñiguez.
Chapter 6 The Field Effect Transistor
EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs.
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Metal-Oxide-Semiconductor (MOS)
EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Digital Integrated Circuits A Design Perspective
Reading: Finish Chapter 6
© Digital Integrated Circuits 2nd Devices VLSI Devices  Intuitive understanding of device operation  Fundamental analytic models  Manual Models  Spice.
Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;
Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.
MOSFET Cross-Section. A MOSFET Transistor Gate Source Drain Source Substrate Gate Drain.
Extension for High-Voltage Lateral DMOS Transistors
Field-Effect Transistor
ECE 342 Electronic Circuits 2. MOS Transistors
MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.
Analog Layout.
NOTICES Project proposal due now Format is on schedule page
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Norhayati Soin 06 KEEE 4426 WEEK 7/1 6/02/2006 CHAPTER 2 WEEK 7 CHAPTER 2 MOSFETS I-V CHARACTERISTICS CHAPTER 2.
Introduction to FinFet
MOS-AK Group Spring'05, StrasbourgApril 8, 2005 B. Diagne, F. Prégaldiny, F. Krummenacher, F. Pêcheux, J.-M. Sallese and C. Lallement InESS / EPFL / LIP6.
Norhayati Soin 06 KEEE 4426 WEEK 3/2 13/01/2006 KEEE 4426 VLSI WEEK 3 CHAPTER 1 MOS Capacitors (PART 2) CHAPTER 1.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab 7 MOSFET Parameters.
1 Fundamentals of Microelectronics  CH1 Why Microelectronics?  CH2 Basic Physics of Semiconductors  CH3 Diode Circuits  CH4 Physics of Bipolar Transistors.
Numerical Boltzmann/Spherical Harmonic Device CAD Overview and Goals Overview: Further develop and apply the Numerical Boltzmann/Spherical Harmonic method.
Comparative Analysis of the RF and Noise Performance of Bulk and Single-Gate Ultra-thin SOI MOSFETs by Numerical Simulation M.Alessandrini, S.Eminente,
ELECTRONICS II VLSI DESIGN FALL 2013 LECTURE 4 INSTRUCTOR: L.M. HEAD, PhD ELECTRICAL & COMPUTER ENGINEERING ROWAN UNIVERSITY.
Junction Capacitances The n + regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram. Planar junctions.
EE141 © Digital Integrated Circuits 2nd Devices 1 Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje.
CMOS Analog Design Using All-Region MOSFET Modeling 1 Chapter 11 MOSFET parameter extraction for design.
Influence of carrier mobility and interface trap states on the transfer characteristics of organic thin film transistors. INFM A. Bolognesi, A. Di Carlo.
The threshold voltage for long channel transistors V T0 is defined as: Eindhoven MOS-AK Meeting April 4, 2008 Eindhoven MOS-AK Meeting April 4, 2008 Accurate.
Structure and Operation of MOS Transistor
Development of an analytical mobility model for the simulation of ultra thin SOI MOSFETs. M.Alessandrini, *D.Esseni, C.Fiegna Department of Engineering.
EE141 © Digital Integrated Circuits 2nd Devices 1 Lecture 5. CMOS Device (cont.) ECE 407/507.
IEE5328 Nanodevice Transport Theory
EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design.
MOSFET Structure p-Si n+ L Source Gate Drain Field Oxide Gate Oxide
COMPACT SMALL-SIGNAL MODELLING OF MULTIPLE- GATE MOSFETs UP TO RF OPERATION Benjamin Iñiguez*, Antonio Lázaro*, Oana Moldovan*, Bogdan Nae* and Hamdy A.
HO #3: ELEN Review MOS TransistorsPage 1S. Saha Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended.
Short-channel Effects in MOS transistors
EE201C : Stochastic Modeling of FinFET LER and Circuits Optimization based on Stochastic Modeling Shaodi Wang
MOSFET Current Voltage Characteristics Consider the cross-sectional view of an n-channel MOSFET operating in linear mode (picture below) We assume the.
EE141 © Digital Integrated Circuits 2nd Devices 1 Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje.
CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 2.
Nano-Electronics and Nano- technology A course presented by S. Mohajerzadeh, Department of Electrical and Computer Eng, University of Tehran.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) allow high density and low power dissipation. To reduce system cost and increase portability,
Joshua L. Garrett Digital Circuits Design GroupUniversity of California, Berkeley Compact DSM MOS Modeling for Energy/Delay Estimation Joshua Garrett,
Nano and Giga Challenges in Microelectronics Symposium and Summer School Research and Development Opportunities Cracow Sep , 2004 Afternoon 11: Nanotechnology.
Principles of Semiconductor Devices ( 집적 회로 소자 ) Principles of Semiconductor Devices ( 집적 회로 소자 ) Hanyang University Division of Electronics & Computer.
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University
The MOS capacitor. (a) Physical structure of an n+-Si/SiO2/p-Si MOS capacitor, and (b) cross section (c) The energy band diagram under charge neutrality.
Microelectronic Circuit Design McGraw-Hill Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock.
EE314 IBM/Motorola Power PC620 IBM Power PC 601 Motorola MC68020 Field Effect Transistors.
High Frequency Compact Noise Modelling of Multi-Gate MOSFETs
INTRODUCTION: MD. SHAFIQUL ISLAM ROLL: REGI:
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
Hamdy Abd El-Hamida, Benjamin Iñigueza, Jaume Roigb
A Fully Physical Model for Leakage Distribution under Process Variations in Nanoscale Double-Gate CMOS Liu Cao Lin Li.
Semiconductor devices and physics
Beyond Si MOSFETs Part IV.
Frequency response I As the frequency of the processed signals increases, the effects of parasitic capacitance in (BJT/MOS) transistors start to manifest.
Presentation transcript:

Analytical 2D Modeling of Sub-100 nm MOSFETs Using Conformal Mapping Techniques Benjamin Iñiguez Universitat Rovira i Virgili (URV), Tarragona, E-43001, SPAIN, Jarle Østhaug, Tor A. Fjeldly UniK- University Graduate Center, N-2027 Kjeller, NORWAY,

n Need of new compact MOSFET modeling concepts n The behavior of sub-100 nm MOSFETs is critically determined by physical mechanisms that are not observed in larger devices. n To allow circuit designers to use the potentials of sub-100 nm technology, these mechanisms must be formulated and implemented into CAD tools.

n Need of a 2-D compact model n The present MOSFET standard models are based on a 1D theory, initially developed for long-channel devices. n Short channel effects have been progressively included (as the feature size has been shrunk down) using additional equations (often empirical). n This has resulted in an enormous increase of the number of parameters.

n Purpose of our compact modeling work n We present a new modeling approach for nanoscale MOSFETs, in order to derive a model based on a careful consideration of device physics. n The scalability property is therefore inherent to the model, therefore provoking a dramatic reduction of the number of parameters with respect to standard models.

n New 2D approach n Our new approach is based on a self-consistent solution of the 2D distribution of the longitudinal electrical field in the device. n Using this approach, short-channel effects and scaling properties are intrinsic to the model. n As a consequence, only a minimum set of parameters with clear physical meaning is needed, and a close accord is established with the fabrication process. n This 2D strategy allows to obtain accurate scaling properties of key parameters, such as threshold voltage and subthreshold current.

2D Strategy n Our method is based on separating the 2D potential distribution in the depletion region under the gate into that corresponding of a 1D Poisson’s equation and that of a Laplacian with well defined boundary conditions. n The Laplacian equation is solved using conformal mapping. n Our method has been applied to classical and SSR bulk MOSFETs n The method can easily be adapted to SOI MOS structures (including DG MOSFETs and FinFETs)

2D Strategy n We consider a bulk MOSFET in which the contact regions are approximated by rectangular boxes and the potential distributions in the drain and source depletion regions are calculated using Poisson 1D. n The MOSFET structure is split into three regions. In region 1, under the gate the 2D potential distribution is separated into a component corresponding to 1D Poisson’s equation and a Laplacian. n The potential distribution has to be determined from the normal electric field E n (x) which points to region 1 from the channel. It is split into a contribution E 0 coming from a 1D analysis and a contribution E 2D (x), coming from a 2D analysis. n Once E n (x) is determined, we will be able to obtain the potential in the channel, which in turn, will allow us to derive the threshold voltage V T and the subthreshold current I sub

2D Strategy Schematic MOSFET geometry Boundary conditions for the Laplacian of Region 1.

Conformal mapping n To solve the Laplacian, we perform conformal mapping of region 1 into the upper half of the (u,v) complex plane (using Schwartz-Christoffel transformation) n It will be easier to find in that plane the potential distributions, because of the relative simplicity of the boundary conditions in it.

Conformal mapping Along the u-axis:

Conformal mapping n This mapping, together with some approximations, allows us to obtain an analytical expression of the component E 2D (u) of the Laplacian, which results in an analytical expression of E 2D (x). n Therefore, we obtain an expression of the potential distribution in the channel, which allows us to derive analytical expressions of the threshold voltage and the subthreshold current

Results Comparison between experimental (symbols) and modeled (solid lines) results. Bulk MOSFETs with N s = 2x10 17 cm -3 and t ox = 8.6 nm (a) Threshold voltage variation with V DS (b) Threshold voltage variation with channel length at V DS =0.05 V. (a) (b)

Results Model calculations of the channel potential relative to the substrate for V DS = 0.05 V and 3 V for gate lengths of 210 nm and 250 nm and t ox = 8.6 nm Model calculations of the channel potential in 70 nm SSR MOSFET relative to the substrate for (a) V DS = 1.6 V at V GS = 0 V (lower curve), 0.1 V (middle curve), and 0.31 V (upper curve),

Results Measured (symbols) and modeled (line) of the subthreshold transfer characteristic for a 250 nm MOSFET with and t ox = 5.6 nm at V DS = 0.05 V. Experimental (symbols) and modeled (lines) subthreshold transfer characteristics for a 70 nm SSR MOSFET with t ox = 3nm. V DS = 0.1 V (lower curve) and 1.6 V (upper curve).

Conclusions n We have developed a closed-form 2D modeling technique for sub-100 nm MOSFETs n The technique is based on conformal mapping, where the 2D Poisson’s equation in the depletion regions is separated into a 1D long-channel case and a 2D Laplace equation. n With a minimal parameter set, the present modeling reproduces both qualitatively and quantitatively the experimental data of deep-submicron and sub-100 nm bulk MOSFETs n Our technique can be extended to SOI MOS structures