Fall Senior Project Presentation Rev :22.00 By: Salem, Ray M. Date: December Title: Micro Mouse Control Systems Topics: Robotics, System Control, FPGA, Communication, Arbitration…

Design Requirement –Traverse & navigate a maze. –Find an optimal route. –Peripheral Controllers. –Abstraction of Hardware. –Communication between Hardware and software.

Sensors Onboard the Micro Mouse

Design Architecture –Controllers embedded into and FPGA (field programmable gate array). –All Controller entities are designed using HDL (Hardware Descriptive Language). –Independent design and testing. –Bottom Up approach.

Relational Block Diagram Sensors –Optical mouse. –Ultra Sonic Sensor. –Infrared Sensor. –Digital Compass. Controllers –Motor Controller. Communications –Super Simple Serial Communication:S^3C. –UART ( universal asynchronous receive transmit ) Memory –Memory Block –Arbitration. –Priority Scheme.

Design Implementation The chosen HDL language is Verilog. All hardware controllers will be targeted to an FPGA specifically Virtex XC300. XESS development board.

Optical Mouse –Provides Highly Accurate location of the current position of the mouse. –All points can now be referenced with a common sensor. –Two axis grid of the maze.

Ultra Sonic Sensor –Frequency Range 40khz. –Sensing Range 3cm – 2M –Discrete Distances. –Acceleration Algorithm.

Digital Compass Philips KMZ51 Compass. –Dual Channel. –Orthogonal Compasses. –Analog Output. AD7829- Analog To digital converter –8 channel. –8bit resolution. Cordic Core –Coordinate rotation by digital computer algorithm.

Motor Controller Texas Instrument control signals –A PWM(pulse width modulated) –Brake –Direction Forward Sw1 & Sw4 Reverse Sw2 & Sw3 Brake Sw1 & Sw3

UART (universal asynchronous receive transmit) 2 Pin Communication. TX & RX 8N2: Eight Data Bits, 115KBaud Rate No parity or error checking 1 or 2 stop bits.

Super Simple Serial Communication - S^3C Asynchronous Serial Communication. Independent of communication media. Write: –Return: Nothing Read: –Return:

Memory Block Single Cycle Volatile memory. Clocked at 25Mhz, Memory Image loaded with bit file to program Memory block with initial memory content. ie. Memory Map.Memory Map

Arbitration. Slave master arbitration scheme. Two entities will require the memory 1.Handle the Communication protocol 2.Handle the data storage for all Peripherals.

Priority Scheme. The device controller requires a priority scheme. –A round robin scheme was implemented. –Entities are allowed A period of 80ns of access to the memory.

Conclusion The Compass development has begun. IR sensors design has begun. Board Layout will begin, with the end of semester. Software development has begun. We are projecting to compete in the Spring 2003 Competition.

Final Thoughts Interested students can get involved. Projects Remaining. For more info you can go the official Micro Mouse web

Infrared Sensor A sensing range of 2-10cm. –Will only output true or false if a wall exist.